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Power the Future with us! At SolarEdge (NASDAQ: SEDG), we're a global leader in smart energy technology, with over 3,000 employees, offices in 34 countries, and millions of installations worldwide. Our innovative solutions include solar inverters, battery storage, backup systems, EV charging, and AI-based energy management. We're committed to making clean, green energy the primary power source for homes, businesses, and beyond. With the growing demand for electricity, the need for smart, clean energy sources is constantly rising. SolarEdge offers amazing opportunities to develop your skills in a multidisciplinary environment, covering everything from research and development to production and customer supply. Work with talented colleagues, tackle exciting challenges, and help create a sustainable future in an industry that's always evolving and innovating. Join us and be part of a company that values creativity, agility, and impactful work. We are looking for a Test Technician to join our R&D HW Battery Group. This role will involve working with cutting-edge technologies and contributing to the development of innovative energy storage solutions. What you will be doing:
* Electrical lab testing – Thermal tests, performance tests, PCBA tests ,debugging ,FA and etc (manual and automatic testing).
* Infra. supporting – Building of testing setups, cables, and mechanical assemblies
* Assist the team in the assembly of the product for all needed tests and lab activities.
* Work closely with other departments in order to promote the product.


Country:
Israel

City:
Herzliya

we are looking for a Senior Core Datapath Engineer.
Roles and Responsibilities:
Design, develop, and enhance I/O subsystems, virtualization, kernel programming, and memory management for cutting-edge system software products.
Drive performance optimization, and efficient memory management.
Perform in-depth debugging, triaging, and resolution of user and kernel-level, performance profiling, and memory-related issues.
Develop innovative solutions, addressing challenges in virtualization, multithreading, and hardware-software interaction.
Explore and implement new methodologies fostering continuous improvement and innovation.
Proactively identify bottlenecks in system design, and recommend and implement robust, scalable solutions.
Stay updated on evolving trends in kernel development, design, and virtualization technologies to bring innovative practices to the team.
Troubleshoot and optimize complex I/O and kernel features to enhance performance, scalability, and reliability.
Collaborate with cross-functional teams to align on design goals and ensure seamless integration with the system architecture.
Exhibit flexibility in taking on new or related tasks, showcasing adaptability and a proactive, problem-solving mindset.
Provide technical leadership in architecture design, problem-solving, and decision-making across complex technical domains.
Lead technical discussions, design reviews, and decisions on critical system challenges, driving the adoption of innovative solutions and best practices.

we are looking for a Director of AI.
The Director of AI will lead the companys AI organization, including algorithm development teams, embedded algorithm engineers within product squads, and the Data Operations team.
This role combines strategic leadership with execution ownership, driving the development, deployment, and continuous improvement of AI-powered products across power transmission, border security, and critical infrastructure monitoring.
The Director of AI is accountable not only for algorithm innovation, but also for ensuring successful production deployment and measurable customer impact. This leader will establish a customer-first culture across the organization, aligning AI development priorities with customer needs, product objectives, and business outcomes.
The ideal candidate is a visionary yet execution-oriented leader who can bridge cutting-edge AI research with scalable production systems, build high-performing teams, and deliver measurable customer value.
Success in this role will be measured not only by algorithm performance, but by the ability to deliver AI capabilities into production and generate measurable value to our customers.
What Youll Do:
Lead the AI group, including algorithm development teams, embedded algorithm engineers, and data operations.
Build and mentor high-performing teams, fostering a culture of ownership, collaboration, continuous improvement, and customer focus.
Define and execute the AI roadmap in alignment with company strategy, customer needs, and product objectives.
Lead the development and deployment of AI, Machine Learning, Deep Learning, and Signal Processing solutions.
Own the full AI lifecycle, from research and experimentation through production deployment, monitoring, and continuous optimization.
Lead the Data Operations function, ensuring efficient annotation, labeling, and quality processes that support AI development.
Partner closely with Product, Engineering, and business leaders to maximize AI impact across the organization.
Engage with customers and stakeholders to understand challenges, identify opportunities, and drive measurable business value.
Communicate AI strategy, progress, opportunities, and risks to executive leadership.
Contribute to company strategy, product direction, and technology leadership.

We are looking for a talented, self-driven, and hands-on DSP Researcher to join R&D team.
In this role, you will research and develop next-generation distributed fiber-optic sensing technologies, focusing on signal processing, system modeling, simulations, and experimental validation. Working at the intersection of physics, electro-optics, fiber-optic sensing, and DSP, you will transform complex physical phenomena into robust sensing solutions for real-world applications.
You will tackle challenging physical and algorithmic problems, contribute to cutting-edge sensing products, and collaborate closely with multidisciplinary R&D teams.
This role is ideal for someone who thrives in a fast-paced environment, enjoys working across disciplines, and is excited to take ideas from research and lab validation to large-scale deployment.
What Youll Do:
Conduct experimental and theoretical R&D for next-generation distributed fiber-optic acoustic sensing systems.
Develop, implement, and validate DSP algorithms for coherent optical sensing systems.
Build end-to-end expertise across the full sensing pipeline, including optical signal generation and propagation, coherent detection, signal acquisition, DSP, and advanced data analysis.
Design and run laboratory experiments to validate new concepts, improve system performance, and support current and future product generations.
Develop simulations, models, and analysis tools using Python and/or C++ for lab experiments, field data analysis, signal processing, and system-level performance evaluation.
Work with field experiment data to identify performance gaps, validate models, and improve sensing capabilities.
Collaborate with R&D teams across disciplines to develop, validate, and integrate new sensing capabilities.
Communicate complex technical concepts clearly to both technical and non-technical stakeholders.

We are looking for a talented, self-driven, and hands-on Electro Optics Systems Engineer to join R&D team. In this role, you will develop and advance next-generation distributed fiber-optic acoustic sensing (DAS) systems, combining electro-optic system design, performance modeling, simulations, experimental validation, and field data analysis.
You will tackle complex physical and engineering challenges, contribute to next-generation product development, and collaborate closely with multidisciplinary teams to bring innovative sensing technologies from concept to real-world deployment.
This role is ideal for someone who thrives in a fast-paced, hands-on R&D environment, enjoys working across disciplines, and wants to see their work translate into real-world impact.
What Youll Do:
Lead experimental and theoretical R&D efforts for the development of next-generation distributed fiber-optic acoustic sensing systems.
Design, evaluate, and optimize electro-optic interrogation systems for distributed acoustic sensing applications.
Develop system-level models and simulations for optical signal generation, fiber propagation, coherent detection, system noise, SNR, and sensing performance.
Build software tools and simulations in Python, C++, or similar languages for system evaluation, signal processing, field data analysis, and performance modeling.
Plan, execute, and analyze laboratory and field experiments to validate system performance and support product development.
Gain unique end-to-end expertise across the full sensing system pipeline, spanning fiber optics, electro-optics, coherent detection, DSP algorithms, and advanced data analysis.
Lead product development activities from ideation and proof of concept through design, qualification, validation, and deployment.
Collaborate closely with multidisciplinary R&D teams, including physicists, software engineers, algorithm developers, and hardware engineers.
Communicate effectively with both technical and non-technical stakeholders, translating complex system behavior into clear insights and actionable recommendations.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.
As a DFT Engineer at our company, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.
Key Responsibilities
DFT Architecture & Strategy
Be part of the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support
Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards
Design and implement DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG for high-end devices
Test Pattern Development & Optimization
Generate and optimize high-quality test and debug patterns for production
Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
Drive test coverage and quality metrics to meet stringent manufacturing requirements
Cross-Functional Collaboration & Methodology Innovation
Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR
Participate in developing and maintaining cutting-edge DFT implementation flows
Automate and improve methodologies using advanced scripting and tools.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.
As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners.You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling our companys products to operate reliably in the worlds most demanding AI and cloud environments.
Key Responsibilities
Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing
Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets
Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp
Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Junior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.
As a Junior ASIC Design Engineer, you won't just build chips - you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams
Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities
Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration.

We are seeking a hands-on highly skilled Engineer to join our Engineering team. This role is focused on solving system-level issues across NPI, manufacturing, and the installed base, while driving continuous improvement in product performance, test methods, integration processes, and overall efficiency.

What will you do?

NPI & Manufacturing Transfer:
Lead transfer of new products from R&D to manufacturing, ensuring production readiness and successful ramp-up.
Define and execute system integration, ATP , and manufacturing qualification processes.
Develop and implement production jigs, fixtures, test stations, and calibration procedures.

System-Level Support & Troubleshooting:
Lead deep-dive investigations into system-level failures or inefficiencies in production, integration, or field environments.
Own and resolve complex issues involving mechanical, electrical, pneumatic, and software interactions.
Introducing calibration, alignment, and test processes in the production line to improve productivity, stability and quality.

Installed-Base Support & Field Performance:
Act as a key escalation point for regional support teams dealing with recurring or critical system issues in the field.
Lead cross-functional task forces to resolve high-impact field failures.
Implement system upgrades and improvements that enhance reliability and performance across the installed base.

Continuous Improvement & Engineering Change Management:
Identify and drive opportunities to improve product robustness, usability, and serviceability.
Lead implementation of design or process changes based on insights from production data, field feedback, and historical lessons learned.
Lead Engineering Change Orders (ECOs), maintain product structure (BOM/product tree).

We are seeking an experienced and hands-on engineering leader
to drive product quality, reliability, and performance across NPI, manufacturing, and the installed base. The role serves as a technical focal point for complex multidisciplinary issues, leading investigations, task forces, and improvement initiatives that enhance product quality , manufacturing readiness, and customer satisfaction.

What Will You Do?

Product Quality and Reliability
Own product quality and reliability performance across NPI, manufacturing, and the installed base.
Define, monitor, and analyze quality metrics, reliability indicators, and field performance trends.
Consolidate quality and performance data from internal operations, contract manufacturers, and field systems into actionable insights and management dashboards.
Lead root-cause investigations and corrective/preventive actions (CAPA) for high-impact product and field issues.
Identify systemic issues, prioritize improvement opportunities, and drive cross-functional execution plans to improve product quality, reliability, and customer experience.

NPI, Manufacturing & Installed Base Support
Drive quality and reliability readiness throughout NPI, validation, and production ramp-up activities.
Lead investigations into complex production, integration, and field failures involving multidisciplinary system interactions.
Partner with Manufacturing, Service, Operations, and Supply Chain teams to improve product stability, serviceability, and operational performance.
Drive implementation of calibration, alignment, validation, and test methodologies that improve quality, consistency, and manufacturing efficiency.
Support contract manufacturers and production teams in resolving critical technical and quality-related challenges.

Continuous Improvement & Change Management
Lead engineering improvement initiatives based on production performance, customer feedback, reliability data, and field experience.
Drive product robustness, manufacturability, serviceability, and lifecycle performance improvements.
Own execution of Engineering Change Orders (ECOs), product structure management, and change implementation through CCB processes.
Lead periodic product performance reviews and drive closure of improvement actions across functions.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Junior Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.
As a Junior Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Physical Implementation & Execution
Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity
Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration
Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.
As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Physical Implementation & Execution
Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity
Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration
Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we are seeking a motivated Physical Design Student to join our founding local engineering team.
This is a unique opportunity to kickstart your career in the semiconductor industry. Working alongside senior industry veterans, you will gain hands-on experience in backend execution and advanced methodologies for cutting-edge chips that power the world's largest AI clusters. If you are passionate about silicon hardware, eager to learn, and thrive on solving complex engineering challenges, this role offers the perfect bridge between your academic studies and a high-impact career.
Key Responsibilities
Guided Implementation & Learning
Partner with and learn from senior engineers to support the physical implementation journey, including synthesis, floorplanning, Place & Route (P&R), and Clock-Tree Synthesis (CTS)
Assist in macro-level implementation and develop hands-on skills in complex layout routing
Participate in deep-submicron process challenges under close professional mentorship
Signoff & Design Integrity Support
Assist in running engineering checks for design integrity, including Static Timing Analysis (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Learn to apply Logic Equivalence Checking (LEC) to help guarantee design correctness
Gain exposure to the rigorous flows required to ensure first-pass silicon success
Scripting & Cross-Functional Collaboration
Leverage and develop scripting tools to automate repetitive tasks and optimize the engineering environment
Collaborate with Architecture, Design, and DFT teams to understand how different chip design disciplines intersect
Actively participate in team reviews and technical discussions to ramp up backend methodologies.