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Key job responsibilities
* Daily involvement in all aspects of physical design chip development (RTL2GDS), including floorplanning, synthesis, clock tree synthesis, place and route, static timing analysis, power and noise analysis, physical verification testing, and equivalence checks.
* Being actively engaged in design-backend convergence aspects and defining timing constraints.
* Taking full end-to-end responsibility for the physical design of macro and cluster-level blocks, according to specifications, under challenging constraints, with focus on optimizing power, area, and performance.
* Participation in the development of design flows, using a variety of EDA tools and vendors such as Synopsys and Cadence.
* Engaged in defining implementation and signoff methodologies.

We are looking for a talented Development Engineer to join our team and take part in building innovative software solutions in a dynamic and challenging environment.

Location: Ramat Hachayal, Tel Aviv. Hybrid option once a week.

we are looking for a Logic Design Engineer.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

Key job responsibilities
* Design and implement advanced Design-for-Test (DFT) architectures for complex semiconductor platforms.
* Develop high-quality test and debug patterns ensuring robust performance.
* Conduct comprehensive static timing analysis across multiple DFT modes.
* Verify intricate DFT logic and components with precision and creativity.
* Support silicon bring-up and device diagnostic processes.

Your day will be filled with complex problem-solving and collaborative innovation. You'll work alongside world-class DFT engineers in a dynamic environment, developing semiconductor technologies that support global cloud infrastructure. Our team thrives on creativity, technical excellence, and continuous learning.

we are looking for a Junior Physical Design Engineer.
You'll be joining our Physical Design team , which is at the center of the silicon development . Our engineers deal with all chip design aspects: definition, architecture, micro-architecture, design, verification, signoff and validation.
We use the latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

We are looking for talented Software Development Engineers to join our teams in Tel Aviv or Haifa and work on low-level software development. You will be building the foundational software layers that sit closest to the hardware - enabling high performance, reliability, and efficiency for AWS services at an unprecedented scale.

This is an opportunity to work in a deeply technical environment where your code runs on custom-designed silicon, directly impacting the performance and cost of cloud infrastructure used by millions of customers worldwide.

Design, develop, and optimize low-level software including device drivers, firmware, and hardware abstraction layers.

Collaborate closely with hardware design teams to define hardware-software interfaces and bring-up new silicon.

Write performance-critical systems software in C/C++ that operates under strict latency and resource constraints.

Debug complex hardware-software interactions.

Contribute to system architecture decisions and define software design patterns for next-gen chip features.

Develop and maintain automated test frameworks to validate functionality and performance at scale.

Participate in code reviews and drive engineering best practices within the team.

Lead verification for advanced ASIC/FPGA designs in a top-tier R&D team developing high-performance network interface solutions and customer-focused hardware.

Location: Tel Aviv office or our Beer Sheva office, which is located next to the train station



Responsibilities:
Drive verification of complex, high-speed ASIC/FPGA designs
Define and implement advanced verification methodologies
Collaborate with architecture, software, and validation teams
Mentor engineers and promote technical excellence
Work with technologies like high-speed interfaces, network processors, and SoCs

We're looking for curious minds who think big and want to define tomorrow's technology. At Amazon, you'll grow into the high-impact engineer you know you can be, supported by a culture of learning and mentorship. Every day brings exciting new challenges and opportunities for personal growth.

Key job responsibilities
- Collaborate and communicate effectively with experienced cross-disciplinary Amazonians to design, build, and operate innovative products and services that delight our customers, while participating in technical discussions to drive solutions forward.
- Design and develop scalable solutions using cloud-native architectures and microservices in a large distributed computing environment.
- Participate in code reviews and contribute to technical documentation.
- Build and maintain resilient distributed systems that are scalable, fault-tolerant, and cost-effective.
- Leverage and contribute to the development of GenAI and AI-powered tools to enhance development productivity while staying current with emerging technologies.
- Write clean, maintainable code following best practices and design patterns.
- Work in an agile environment practicing CI/CD principles while participating in operational responsibilities including on-call duties.
- Demonstrate operational excellence through monitoring, troubleshooting, and resolving production issues.

We are looking for Software Automation Engineer to help us develop a semiconductor platform based on a revolutionary architecture.

Take part in the development of products within a disruptive system architecture. Youll have the opportunity to work in a dynamic, open, fast-paced environment, developing the technologies that power the worlds largest cloud provider. AWS provides a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world.

Key job responsibilities
As Software Automation Engineer, you'll be responsible for creating ML (Machine learning) and HPC (High performance computing) automation and tools, create CI/CD flows and implement effective dashboards with high scale.

we are looking for a Senior Physical Design Engineer.
Your Impact:
You'll be part of the team, which is at the heart of software and ASIC design efforts.
You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

we are looking for a Senior Asic Design.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

Required Software Engineer, ML (Technical Leadership)
The financial risk management (FRM) machine learning principal will be the most senior machine learning engineer and strategist for financial risk. The principal will enable the risk organization to deliver significant lift over current long range objectives for friction and leakage through the generation of new Machine Learning opportunities for the organization and support of successful delivery of the risk management ML architecture. This person will partner closely with the FRM engineering leader (Director level) and be part of our risk management leadership circle.
Software Engineer, ML (Technical Leadership) Responsibilities
Address core business and technical machine learning opportunities: elevate the existing portfolio of machine learning solutions to be state-of-the-art for minimizing our financial losses (due to leakage, good revenues loss and friction). Following are a few examples of technical and business problems we aim to address. - Provide a solution for optimizing the risk machine learning model ensemble (covering the entire end-to-end advertiser funnel including detection, decisioning, enforcement and remediation) through optimization of the current model portfolio and individual models. - Minimize the impact of the prolonged financial fraud feedback loop. - Improve models measurement and performance. - Optimize data/label strategy. - Optimize balance between specific targeted model strategy and broad umbrella model strategy to optimize for short and long term benefits
Lead Research and Introduction of Advanced Technologies: - Collaborate with Financial Integrity's senior ML Engineers to lead the research and introduction of deep learning and Large Language Model (LLM) technologies. - Remain current on industry-wide advancements in ML and introduce relevant advancements in Financial Risk Management
Collaborate on Next-Generation ML Architecture: - Work closely with financial harms principals and risk management tech leads to deliver the next-generation ML architecture for our risk management system. - Collaborate with Principal ML engineers from across the company to adopt best industry and our practices within the FRM team. - Resolve or mitigate design dilemmas, balancing business and technical trade-offs. - Identify and initiate opportunities for collaboration and impact with other organizations
Identify and Initiate New Business Opportunities: - Collaborate with our FinTech, Central Integrity and Core Ads Growth partnerships to identify and initiate new business opportunities based on third-party capabilities. - Conduct proof of concept for different opportunities and initiate integrations to enhance business performance
Grow Other Senior ML Engineers - Actively invest in the growth of other senior ML engineers through goal-driven formal and informal mentorship. Provide regular feedback to other engineers regarding their technical work.

We're looking for exceptional engineers to join our Pre-Silicon Verification team - the team that sits at the very center of the chip development lifecycle. Verification at Annapurna Labs isn't a downstream checkpoint - it's the connective tissue that spans the entire product journey:
It starts at product definition - we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written.
It extends into software - we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack.
It reaches into physical design - we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality.
It closes the loop - from spec to silicon, our verification touches every team and every stage of chip development.

We are seeking a highly effective Supply Chain Planner to manage a semiconductor supply chain with multiple products in close collaboration with internal and external cross-functional teams. This role encompasses both production planning and New Product Introduction (NPI) planning responsibilities.
This dynamic role requires interaction with suppliers and internal stakeholders to manage production planning, NPI launches, material movements, supplier coordination, and support for engineering/pre-production builds. The successful candidate will communicate product status and open issues, report available-to-promise, prioritize demand management, and provide strategic direction for supply chain optimization.

Key job responsibilities
Own production plans of multi production lines.
Suppliers management with daily communications providing direction.
Direct communication with customers over demand forecasts and own timely delivery commitments.
Manage NPI from concept to production - Strategic supplier selection, Balance capacity across NPI and volume production.
Plan qualifications and NPI timelines, pilot builds, BOM material availability.
Analyze constraints and present mitigation plans and status to leadership.
Develop long-term supply strategies and contingency plans.
Collect and analyze supply chain data; maintain KPIs and dashboards
Release procurement of the BOM components.
Manage materials across foundries, assembly/test houses, and contract manufacturers, Track WIP, inventory, shortages.

We are seeking a high-driven, results-oriented multidisciplinary orchestrator to act as the primary catalyst for our development infrastructure. In this role, you will operate at the critical intersection of product strategy, hardware engineering, and lab operations, serving as the connective tissue that aligns disparate teams under a unified goal. You will be responsible for driving cross-functional alignment across the organization, effectively managing stakeholders with differing ownership to ensure infrastructure roadmaps scale alongside product milestones. This position requires a self-starter comfortable pushing for success in ambiguous environments, where you will translate high-level strategy into the tactical execution of the physical and virtual ecosystems that power our development lifecycle.
Your Impact:
You will own the end-to-end lifecycle of infrastructure projects, ensuring that our Sanity Test Beds and development environments are optimized to meet aggressive product launch timelines. By bridging the gap between engineering roadmaps and infrastructure requirements, you will serve as the engine that ensures our teams have the right resources at the right time, regardless of technical or organizational complexity.