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we are seeking a skilled and motivated automation practical engineer (operator) with 5 years of experience to join our group. in this role, you will play a crucial part in ensuring the reliability and performance of our products through comprehensive automated testing and taking full responsibility for regression cycles. you will work with a variety of operating systems and projects, ranging from drivers to user applications, and will develop new automation frameworks for regression testing in complex environments.
what youll be doing:
monitoring & debugging: monitor and debug night regression runs, quickly identifying and resolving issues to maintain continuous testing cycles.
automation development: design, develop, and implement automated testing frameworks for regression testing, particularly over a simulated virtual machine environment, to ensure the stability and performance of our products.
complex configuration management: gain a deep understanding of complex customer configurations to tailor and optimize automated TEST environments.
multi-os environment: manage and execute tests across multiple operating systems, including Linux, windows, VMware, and freebsd, to ensure comprehensive coverage and compatibility.
cross-project collaboration: work across various projects, from low-level driver testing to high-level user application verification, ensuring that all components of the product meet our stringent quality standards.

our company is looking for best-in-class physical design cad engineer to join our outstanding networking silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
you will be in charge of developing physical design, synthesis, sta and logic eq methodologies for implementation of networking chips and socs.
work closely with block owners. full chip sta engineers and project managers to assure high quality and timely convergence.
come up with unique and creative solutions to the state of the art physical design problems that are needed for our chips.
additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, p&r, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.

in this role, you will play a critical part in advancing cumulus Linux, a leading networking operating system and a cornerstone of the ai factory - the next-generation data center designed to power the training, fine-tuning, and deployment of ai models at scale. you will work closely with cumulus Linux design and architecture teams while gaining deep insights into nvidias products and technologies.
what youll be doing:
manage, mentor, and guide a team of software developers.
oversee the design, implementation, and maintenance of scalable automation frameworks, while remaining hands-on with software development and debugging.
drive timely, high-quality feature delivery.
collaborate with global, cross-functional teams to identify, track, and resolve issues.
analyze customer-reported issues, identify TEST gaps, and ensure robust regression coverage.
work with continuous integration systems and regression tools.
foster a culture of innovation, quality, ownership, and accountability.
support team members with career development plans and achievable growth goals.

are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? our engineering team works on groundbreaking innovations involving crafting creative solutions for dft architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. we are looking for an experienced dft engineer to join the atpg team. the position includes taking part in development of the next generation dft technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
 
working on the most advanced technologies and complex products, our dft solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
 
what youll be doing:
you will be in charge of state of the art design for TEST /atpg flows and implementation
take full atpg ownership end to end on a project, from arch & planning to pattern generation, verification and post silicon bring up and diagnosis.
inventing and maintaining automation flows that provide the short TEST time to production

we are now looking for a senior chip design rtl design engineer for the switch silicon group.
as a chip design engineer networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
work in a combined design and verification team which develops some of the switch silicon core units.
plan and design rtl units / blocks according to arch & micro arch specifications under challenging constraints with high orientation to power, area, and performance.
build reference models, verify and simulate chip blocks/entities according to specifications.
work closely with multiple teams within organizations such as architecture, micro- architecture, and fw.

this senior role places you at the center of innovation, where you will have a direct impact on our business and technology by solving sophisticated technical challenges. its a unique opportunity to shape our technology and empower customers to build the supercomputers and ai fabrics of tomorrow.
what you'll be doing: lead the architectural design, development, and optimization of cutting-edge pcie firmware, using ai-driven modeling and insights to deliver exceptional performance.
serve as a trusted technical expert by investigating, debugging, and resolving challenging pcie firmware issues for our most important customers.
collaborate closely with our chip design, verification, software, and Architecture Engineers to find root causes and develop robust, long-term solutions.
champion the integration of ai-assisted diagnostics and generative ai tools across the entire development lifecycle to boost team productivity and innovation.
translate customer needs and field data into actionable feedback that directly shapes the future of our products.

looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part inflows development.

we are looking for an enthusiastic software engineer to join our ai networking acceleration team, to work on a groundbreaking open-source library, using hardware offloads, gpu kernels and rdma network cards. our product is a performance-oriented low-level infrastructure, crafted to change the way inference works.
we thrive as a team in a deeply strong environment, and we're passionate about innovation. the rewards are sweet and include working with some of the brightest people in the industry, an aggressive compensation plan that rewards top performers, and the opportunity to collaborate on products that transform daily the way people work and play.
what you'll be doing:
developing a highly optimized inference framework
running on the worlds largest supercomputers and data centers.
the work environment is dynamic and challenging as our employees work on innovative, next-generation products at the forefront of technology in terms of performance, scalability, and features.

we are looking for a chip-design Verification engineer to join our switch silicon team. as a chip design Verification engineer at םור networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
work in a design and verification team that develops the Front-End design for the switch silicon and the gpu.
develop verification components and reference models, as well as verify and simulate chip blocks according to specifications under challenging constraints with a high orientation to power, area, and performance.
work closely with multiple teams within organizations such as architecture, micro- architecture and fw.

we are hiring a senior pcie firmware to the chip design pcie firmware team. you will be joining a team whose primary mission is to work on groundbreaking technology network adapters and build the core technology of the next generation devices in a wide range of fields - low-level C layer between hw and fws, automation challenges, and Python testing environment.
what youll be doing:
implement fw and verification features in a pre and post silicon environments in the pcie technology
collaborate with other teams in the pcie group, software, and architecture teams to define and craft legacy and new low-level firmware verification methods
improve the existing automated process

looking for a best-in-class chip design - hw emulation senior engineer to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a significant part in emulating our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company. join world-class emulation team in israel. our focused team takes switches/nics/socs designs and program the emulators to behave like our silicon. are you ready to take on interesting problems and craft solutions? come check out our team.
what you will be doing:
the main responsibility is emulation and prototyping of complex chip designs. this includes defining the methodology and crafting the infrastructure needed to quickly take large chips into hardware emulation platforms.
the job also requires close collaboration with design, verification, and software engineers to enable Embedded software and application software development.
connecting emulator/fpga based solutions to real external h/w or virtual targets, taking care of complex testbench and different protocols.
this is a role for a versatile engineer that includes rtl design, verification, fpga partitioning and implementation, scripting, and lab-based bring up of the design.

our company networking system validation group is growing, and we are hiring a junior switch system Validation engineer. as a member of the team, you will take part in our core network projects which drive the growth of the company, tech and business wise. you'll gain networking and switch u-arch knowledge while helping validate, optimize, and debug devices in different areas like quality-of-service, performance, logic correctness, and ai features. 
you will work closely with logic design, circuit design, and architects to ensure successful product development with aggressive product cycles, in both pre and post silicon stages. 
you should have a good grasp of software development in different fields, such as Python scripting, Embedded software, and device firmware. it's important to have experience in a complex emulation environment and show a strong interest in creating, doing, and improving silicon validation plans. 

what you will be doing: 
work in a combined design and verification team specializing in switch full chip works
understand the switch architecture and build on  TEST plan accordingly 
develop full chip  TEST collaterals/suites, maintain regressions, debug failures and sign-off coverages 
maintain TEST suites to facility emulation and/or silicon platforms checkout as well

seeking an experienced software engineer to join the networking switch sw group, developing the switch operating system (nvos). key role in developing the nvos is critical for next-gen networking tech for hpc data centers. are you passionate about working on innovative technologies? then we want to hear from you!
what you'll be doing:
owning and leading the nvos including development, testing flow and product life cycle.
as a senior software engineer at nvidia, you will use your expertise in C ++ and Python to develop nvos features and support new products.
lead nvos integrations with fw, hardware, and production teams.
support internal and external customers for any nvos related items.

our company is looking for an asic design engineer to join the dft design team and develop the next generation dft technologies.
as a design engineer in the dft design team at our company, you will participate in definition and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and sophisticated products, our dft solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for defining, coding and integrating sophisticated dft components into various projects and using state-of-the-art technologies.
as a member of our dft design team, you will participate in defining various dft features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

we are now looking for a motivated chip architect to use your creativity to work on the connectx network adapter with the highly inventive and knowledgeable team.
what you'll be doing:
define the network adapter chip architecture end to end from the market requirements through design and all product life cycles (post/pre-silicon, on deployments). work with related industry standards & customers on deploying your tech.
collaborate with teams across teams (physical design, logic design, system software, firmware, applications)
work on proof of concepts and advance development projects.
perform research and analysis for current and future architectures.
craft product design specifications.
serve as a focal point within the organization and distribute the knowledge that you acquire.