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join the department's system integration and QA team
take a significant role as part of multi-disciplinary project teams, filling roles of system integration, QA, testing, and deployment support
define testing scenarios to systems designed by the department
conduct testing procedures including lab and field experiments
define, develop and augment automation to improve the efficiency of testing

serve as the main technical integrator between engineering disciplines, including hardware, Embedded software, Full-Stack software, algorithms, RF, and other relevant domains.
lead system -level definition and architecture of complex multidisciplinary products and features and translate product and operational needs into clear system requirements.
drive cross-disciplinarity technical decisions, architectural trade-offs, and resolution of system -level issues.
ensure consistency between system requirements, detailed design, implementation, integration, and verification.
identify technical risks, gaps, interfaces, and dependencies and drive them toward resolution.
lead system integration, troubleshooting, verification, and validation activities.

Define experimental and theoretical research strategies to characterize light-tissue interactions, optical penetration, and thermal/mechanical effects in biological media.
Design, build, and operate experimental lab setups to investigate photo-induced tissue damage (e.g., dermal and ocular tissue models), defining precise biological damage thresholds and exposure margins.
Serve as the team's foremost authority on laser safety, leading formal laser classification (e.g., IEC 60825, ANSI Z136, FDA CDRH) and product safety compliance.
Translate complex biological damage models and physical limits into actionable system-level specifications, hardware constraints, and operational safeguards.
Define and design system level solutions for safety compliance.
Develop and validate analytical and numerical simulation models (e.g., Monte Carlo light transport, thermal bio-heat equations) to predict tissue response and optical safety margins.
Analyze and report empirical findings clearly, enabling cross-functional engineering teams to make rigorous, risk-informed architecture decisions.
Partner with multidisciplinary teams across hardware, firmware, optics, and human factors to drive feasibility from concept to safe, viable product implementations.

Responsibilities
Lead the biological and physical risk assessment for novel optical concepts, pinpointing exposure limits, hazards, and mitigation pathways.
Conduct hands-on lab experiments combining lasers and biological tissue models to measure, observe, and quantify damage mechanisms under varied irradiation profiles.
Formulate and own the formal laser product classification strategy, defining engineering controls, interlocks, and compliance documentation.
Characterize system-level physical limits and optical delivery parameters (wavelength, pulse duration, fluence, beam profile) to maximize performance while strictly adhering to safety standards.
Author comprehensive safety reports, compliance dossiers, and technical whitepapers to support engineering choices and regulatory alignment.

As a Camera System Engineering EPM, you will:
Own and drive the execution of next-generation camera system programs across our product lines.
Collaborate with electrical, mechanical, optical, and software teams to deliver seamless and innovative imaging solutions.
Navigate ambiguity, solve complex system integration challenges, and lead programs from concept through launch.
Influence product and technology roadmaps by working closely with design, architecture, and operations teams.
Be the voice of the program-communicating milestones, risks, and vision clearly across executive and engineering leadership.
Thrive in a high-energy environment where every day brings a new challenge and a new opportunity to innovate.

As a member of our ML group, you will research and build AI systems that change how our silicon is designed. Many of these problems are still open: the right way to frame the problem isn't known yet, and the data is scarce or noisy.

We are looking for a strong researcher who enjoys working closely with design teams to turn open-ended questions into well-posed research problems, and who wants to see the results used in real projects. Success in this role means models and agents that measurably improve designed chip metrics (Power, Performance, and Area) and design turnaround. You will join a growing team of AI and software engineers working with our chip design teams.

Responsibilities
Research and develop AI methods for the physical design flow, from floorplanning and placement through routing and timing closure, combining predictive models, optimization, and generative AI.
Design and build agentic workflows that connect LLMs to EDA tools, design data, and internal infrastructure, to automate and speed up tasks such as flow setup, debug, design exploration, and analysis.
Work with design teams to turn open-ended problems into well-defined research questions with clear metrics, baselines, and success criteria.
Develop robust AI methods for limited, noisy, or imbalanced data, leveraging domain knowledge and advanced learning techniques.
Own data end to end: extract useful signal from EDA tool outputs and design databases, validate and clean it, and build datasets and benchmarks where none exist.
Run careful experiments and evaluations for both models and agents, and report clearly what works and what doesn't.
Work with software engineers and design teams to bring promising prototypes into production flows, and improve them based on feedback from real projects.
Help shape new research directions as our work grows, follow the AI and EDA literature, and bring relevant ideas to the team.

We are seeking a highly skilled and motivated ML Deployment Engineer to join our on-device AI team. In this role, you will take state-of-the-art machine learning models and make them run efficiently on Apple silicon - compressing, compiling, and optimizing them to deliver intelligent experiences that run entirely on-device, with the performance, power, and privacy our users expect.

Responsibilities
Own the model deployment pipeline from trained checkpoint to on-device execution, ensuring models meet product-quality bars for accuracy, latency, memory, and power.
Apply model compression techniques - quantization (post-training and calibration-based), palettization, pruning, and mixed-precision - and validate the accuracy/size/latency trade-offs of each.
Convert and compile models to the Core ML stack and target the Apple Neural Engine, GPU, and CPU.
Analyze and maximize accelerator (ANE) residency; diagnose why operations are rejected or dispatched to fallback compute units, and work with the graph to resolve them.
Profile end-to-end inference on real hardware, identify bottlenecks, and optimize compute-unit placement, memory footprint, and energy consumption.
Collaborate closely with ML research and applied ML to co-design models that are efficient to deploy and to feed hardware constraints back into model architecture decisions.
Build and maintain tooling and automation for reproducible compression, compilation, benchmarking, and numerical validation.
Stay current with the latest advances in efficient ML inference, model compression, and accelerator architectures.

We are seeking a creative and hands-on Deep Learning Research Engineer to drive model and architecture innovation across our sensing platforms. In this role, you will go beyond off-the-shelf models, exploring novel neural network designs, designing rigorous training and validation pipelines, and translating inventive concepts into clean, high-performance implementations. While our domain deals with physical data, this is an ML-first role: we are looking for a deep learning specialist with strong research intuition, expertise in PyTorch, and the drive to solve non-standard, real-world problems.

Responsibilities
Conceive, design, and implement novel neural network architectures tailored for complex physical sensing, reconstruction, and inverse problems.
Lead end-to-end hands-on research: data preparation, model formulation, training, hyperparameter exploration, and failure-mode analysis.
Build, train, and rigorously validate deep learning models using Python and PyTorch.
Formulate custom loss functions, regularization techniques, and inductive biases that capture domain-specific constraints.
Design comprehensive validation and benchmarking suites to stress-test model robustness, generalization, and scaling behavior.
Propose creative, non-conventional modeling ideas, stay abreast of state-of-the-art DL literature, and rapidly prototype proof-of-concepts.
Collaborate cross-functionally with physicists and optical software engineers to benchmark models against simulated and experimental lab datasets.

We are looking for talented engineers to join our STA team. In this role, you will be working closely with multiple integration teams, like DFT, Top Level PNR, PHY designers and PNR teams.


You will be responsible for:
Develop/support automated block and full chip level signoff flows.
Full Chip Timing/Noise convergence and full signoff for high quality TO
Enable hierarchical Timing flows.
Power optimizations.
Generate block level budget and context for correlation with Full Chip.
Drive custom IP integration and custom timing checks flows.
Close work with Design, DFT, architecture and Power team.

We are looking for a research scientist with an extraordinary theoretical background in machine learning and computational mathematics. This is a foundational theory role: we are seeking someone who truly understands how learning algorithms function from first principles, identifies computational and statistical barriers, and proves what is achievable under information-theoretic constraints.
While knowledge of privacy mechanisms (such as Differential Privacy) and cryptography is a strong advantage, the core priority is deep theoretical maturity in statistical learning, sample complexity, and optimization theory. You will bridge mathematical rigor with practical algorithmic innovation, shaping the next generation of our private machine learning.

Responsibilities
Conduct foundational theoretical research into the limits, bounds, and trade-offs of learning algorithms under privacy, computational, and statistical constraints.
Formulate and prove theoretical guarantees for machine learning models, analyzing sample complexity, generalization error, and convergence rates.
Design, analyze, and benchmark novel privacy-preserving learning algorithms (e.g., DP-SGD, private aggregation, and local/central differential privacy paradigms).
Collaborate with applied research and engineering teams to translate theoretical insights and mathematical proofs into practical, scalable machine learning solutions.
Explore intersections between statistical learning theory, optimization landscapes, and cryptographic primitives.
Author high-impact research papers for publication in top-tier machine learning and theoretical computer science conferences.
Stay at the forefront of foundational ML theory and privacy literature, identifying theoretical bottlenecks and proposing novel avenues of investigation.

The NPI Engineer is positioned at the interface between Engineering R&D and Manufacturing teams - providing technical and operational support throughout the product development and manufacturing lifecycle.
The role is responsible for ensuring product data accuracy, manufacturing readiness and resolving technical challenges encountered during assembly processes.
The position requires a strong technical foundation, attention to detail and a solid understanding of electronic components, PCB assemblies and manufacturing processes.

We are seeking a highly motivated NPI Engineer to support cross-functional Engineering R&D and Manufacturing teams.
The role requires hands-on experience with printed circuit board assemblies (PCBAs), from design through manufacturing and a solid understanding of product lifecycle management, component engineering, and manufacturing operations.
The NPI Engineer will bridge engineering design requirements with manufacturing execution, resolve technical challenges on the assembly floor and support successful product introductions in a dynamic, global environment.

Responsibilities
Support Product Lifecycle Management (PLM), including engineering changes, product data accuracy and configuration control.
Review and maintain Bills of Materials (BOMs), identifying discrepancies and risks.
Support component engineering, including part definition, catalogingd and alternative part evaluation.
Provide technical guidance on Surface Mount Technology (SMT), PCB assembly, and mechanical assembly processes.
Investigate manufacturing and quality issues, define corrective actions, and drive process improvements.
Collaborate with Engineering, R&D, Operations, and Manufacturing teams to ensure production readiness.
Develop and maintain manufacturing documentation, including assembly instructions and production specifications.

Our growing team is looking for a team player with versatile technical skills. You will engage in a cross-functional, collaborative environment that will take your debugging and technical skills to the limit while integrating cutting-edge technologies into our products.
In this role, youll be responsible for bringing groundbreaking wireless connectivity to the world through Wi-Fi, Bluetooth, and more. You will collaborate across departments to help craft wireless solutions that elevate the customer experience with our products and services.

In this role, you will be responsible for:
Work as part of a team to operate a large-scale test automation lab for our multiple products.
Test and integrate SW and HW deliveries from various global R&D teams, including managing, debugging, and failure analysis of automated tests.
Automate manual tasks for the lab and collaborate with technology teams to migrate more setups to the lab.
Constantly improve and innovate our lab procedures, HW setups, and SW tools.
This is a fixed-term position, with the possibility of extension.

As a manager in the RTL/FE CAD team, you have the opportunity to shape the future of chip design and impact our engineers who develop the next generation of our products! You will lead a high-impact team that develops software solutions used by thousands of RTL design and integration engineers globally across all chip families (iPhone, iPad, Mac, Apple Watch, and more).
In this role, you will be a key catalyst in transforming front-end hardware design into a modern, agile discipline. You will spearhead the transition to agentic workflows-redefining how RTL and integration teams operate in the AI era. This role combines deep knowledge of RTL/FE flows with modern software engineering practices, people leadership, and a transformative vision for engineering methodology.

Responsibilities
People Leadership: Lead, mentor, and grow a team of ~20 CAD engineers, driving talent acquisition, technical mentorship, performance management, and career development.
Agentic Flow & Methodology Transformation: Drive the team and broader RTL/FE community toward agentic workflows. Act as an organizational change agent, pioneering modern, agile methodologies that transform daily design and integration practices.
LLM Harness & Agentic Tooling: Own the architecture and execution of the LLM harness for RTL/FE flows (e.g., autonomous violation triage for Lint/CDC/RDC, intelligent connectivity synthesis, and design assist agents). Establish rigorous benchmarks to continually evaluate and elevate workflow accuracy and autonomy.
RTL Integration & Connectivity Tooling: Own end-to-end RTL integration tools, including connectivity generation, SoC assembly automation, IP packaging, and structural checks.
Static Sign-off Checks: Drive methodology, deployment, waiver governance, and sign-off metrics for Lint, CDC, RDC, and related static verification domains.
Roadmap & Milestone Alignment: Define strategic roadmaps and near-term execution plans aligned with multi-project tapeout milestones and long-term organizational goals.
Stakeholder & EDA Vendor Partnership: Collaborate closely with RTL design and integration leads to turn evolving design challenges into robust software solutions. Partner with EDA vendors to resolve escalations and influence tool roadmaps.
Software Excellence: Champion software engineering best practices, modern Python development, scalable cloud architectures, and robust CI/CD infrastructure within CAD.

We are seeking a senior ATE Software Engineer to design, build, and deploy our next-generation automated manufacturing test platform for advanced telecom, high-density switching, and optical networking hardware.
In this role, you will bridge the gap between R&D hardware/firmware teams and high-volume manufacturing lines. You will take ownership of ingesting, refactoring, and consolidating disparate R&D scripts, diagnostic tools, and legacy software into a single, scalable, production-grade test platform.
We expect you to leverage modern AI-assisted development tools and workflows to maximize engineering efficiency, accelerate delivery timelines, and build highly robust, self-healing test automation. You will deploy test stations across global Contract Manufacturers (EMS/ODM), actively stabilize production lines through bring-up and ramp-up, and drive continuous test maintenance and root-cause failure analysis (RCA).
Key Responsibilities
Test Platform Architecture & Software Development:
Design, develop, and productize robust, modular test software frameworks for board-level (PCBA) and system-level manufacturing testing across multiple product lines and manufacturing sites.
Codebase Unification & Refactoring:
Consolidate and standardize R&D diagnostic libraries, silicon validation scripts, and firmware tools developed across various environments (Python, C# / Visual Studio, VB, ATEasy, Linux) into a unified, maintainable test execution engine.
AI-Accelerated Development & Workflow Automation:
Actively integrate Generative AI tools and AI coding agents into your daily workflow to accelerate code conversion/refactoring, automate test case synthesis, generate edge-case validation scripts, and enhance overall codebase resilience.
Production Line Deployment & Stabilization:
Deploy test stations and fixtures to local and overseas EMS/CM production lines. Monitor, debug, and fine-tune test execution during NPI and ramp-up phases until yield, takt time, and test stability targets (CPK / First Pass Yield) are achieved.
Failure Investigation & Intelligent RCA:
Investigate complex system-level and component-level test failures. Utilize advanced log analysis, structured telemetry, and pattern recognition to drive root-cause investigations and implement preventive software/hardware fixes.
Ongoing Test Maintenance & Optimization:
Provide continuous operational Production line support and maintenance, bug fixes, software updates, and station cycle-time optimizations for active mass-production lines.
R&D Collaboration & Test Specification:
Collaborate closely with Hardware, Firmware, and Validation teams during early design phases to define test specifications, drive Design for Testability,
Documentation & Technical Reporting:
Author and maintain comprehensive testing documentation, Standard Operating Procedures (SOPs), test coverage matrices, and detailed failure analysis reports.

We are seeking a highly skilled and experienced multidisciplinary engineer with a strong background in system design to join our team. In this role, you will contribute to our upcoming projects and play a key part in the rapid expansion of the Ethernet market.
As a such, you will be responsible for developing high-speed digital and analog circuit boards used in Ethernet products. Your duties will include designing board schematics, overseeing PCB layout, and conducting lab . Additionally, you will be responsible for evaluating new hardware solutions, providing technical leadership in troubleshooting and reviewing schematics, layouts, and design for manufacturability (DFM), as well as managing components selection.