דרושים » חשמל ואלקטרוניקה » Senior Processor Verification engineer

Required Senior CPU Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
We're the driving force behind groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Required CPU Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
We're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Required Design Verification Engineer, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design Verification Engineer, you will be a part of the Research and Development team to verify digital designs, develop constrained-random test environments and drive system testing to closure. You will collaborate with design and verification teams, manage the verification life-cycle and uncover bugs through corner-case testing.
Responsibilities
Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop and refine random verification environments using SystemVerilog/Universal Verification Methodology (UVM) or Specman to ensure effective test coverage.
Define and implement various coverage measures to capture stimulus and corner-case scenarios.
Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters.
As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You wont just execute tasks; you will define the Formal verification strategy for chips that drive the worlds largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications.
Key Responsibilities
Own and develop formal verification environments from scratch through to sign-off
Apply formal verification methodologies and strategies to prove the correctness of intricate designs
Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements
Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs
Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently
Architect and develop generic, common formal functions and properties to be reused across multiple projects.

We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the Cisco SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.
Your Impact:
Lead and drive DFT verification activities within the Cisco SiliconOne DFT team.
Develop verification plans, environments, checkers, assertions, and coverage models for DFT features.
Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams.
Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features.
Debug complex pre-silicon issues across RTL, verification environments, and DFT logic.
Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV.
Help bridge between general DV methodologies and DFT-specific design and verification needs.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.
As a Senior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified
Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices
Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment.

We're looking for a Senior Design Verification Technical Lead- a design verification technical lead that is responsible for complex SoC sub-system, with cutting edge technology for Graviton server SoC.
It starts at product definition- we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written.
It extends into software- we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack.
It reaches into physical design- we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality.
It closes the loop- from spec to silicon, our verification touches every team and every stage of chip development.

As a Senior Design Verification Technical Lead on the Graviton team, you will be responsible for
leading the verification of complex SoC sub-systems, driving cutting-edge verification
methodologies, and ensuring our next-generation Graviton server SoC meets the highest quality
bar before reaching silicon.

What You'll Do:
- Develop and execute verification plans for IO sub-systems- covering interconnect.
protocols, peripheral interfaces, and system-level integration
- Verify IO sub-system features including interconnect protocols, various accelerators engines.
- C embedded SW programing and SW debug skills
- Build and maintain UVM-based verification environments for IO sub-systems.
- Verify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol compliance.
- Verify the IO virtualization SMMU/TLB operations, page table walks, translation granules, and memory attributes (cache-ability, share-ability).
- Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditions.
- Drive coverage closure using functional coverage models, assertion-based verification, and formal methods where applicable.
- Contribute to performance verification - ensuring micro-architectural
implementations meet performance targets alongside correctness.

The WSSI (Windows Silicon System Integration) team is looking for an experienced Silicon Design Verification Team Lead to lead verification for complex silicon subsystems that are part of advanced solutions delivered in Windows client products.

This is an opportunity for an excellent DV leader to combine people leadership with meaningful hands-on technical contribution. You will lead a silicon engineering team that includes design verification, silicon design, and physical design engineers, while serving as the technical anchor for the team's verification strategy, execution, and quality.

The team works on complex security-oriented silicon subsystems that require rigorous pre-silicon verification and close collaboration with architecture, design, firmware, system engineering, and physical design partners to deliver robust silicon quality.

We are looking for a leader who is passionate about building excellent teams, driving rigorous execution, contributing hands-on to complex verification challenges, and continuously improving verification methodologies - including applying modern AI-assisted techniques to improve productivity, debug efficiency, and verification quality.

Responsibilities
Lead, grow, and mentor a silicon engineering team that includes design verification, silicon design, and physical design engineers, while fostering a culture of technical excellence, ownership, collaboration, and continuous learning.
Own and drive the verification strategy for complex silicon subsystems from planning through execution, closure, and emulation readiness.
Provide substantial hands-on technical contribution and leadership in verification planning, testbench architecture, debug, coverage analysis, regression quality, and verification closure.
Build and promote modern verification workflows, including AI-assisted techniques that improve verification environment development, automation, debug efficiency, coverage analysis, and execution quality.
Define verification plans, quality metrics, regression strategy, coverage goals, and emulation readiness plans aligned with project milestones.
Collaborate closely with architecture, design, system engineering, firmware, and physical design partners to identify risks early, resolve complex issues, and deliver high-quality silicon subsystems.

Required Staff RTL IP/Component Design Engineer, Cloud
About the job
In this role, you will contribute in all phases of complex application-specific integrated circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next-generation of our platforms, we make product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Define the block level design document such as interface protocol, block diagram, transaction flow and pipeline, etc.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, and VHDL), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Support synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Junior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.
As a Junior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified
Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices
Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment.