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דרושים בNishapro
Job Type: Full Time and Hybrid work
We are looking for an experienced and creative Verification engineer to join our Processor Verification Team.

In this role, you will be responsible for verifying the core units of our next-generation processors. You will work closely with the architecture and design teams to ensure functional correctness through advanced verification methodologies, taking ownership of verification environments from planning to coverage closure.
Requirements:
Education: B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering.
Experience: 7+ years of hands-on VLSI verification experience.
Core Expertise: Deep knowledge of SystemVerilog and UVM (Universal Verification Methodology).
Technical Advantages:

Experience in Processors Verification (arithmetic units, control logic) is a significant advantage.
Background in RTL Design or a strong ability to read and analyze Verilog implementation.
Experience with C / C ++ programming is an advantage.
Scripting capabilities ( Python / PERL ) for automation and flow efficiency
This position is open to all candidates.
 
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Location: Hod Hasharon
Job Type: Full Time
our companys innovative processors are designed into the advanced cellular systems of most tear-1 carriers .
We are looking for an experienced and creative Verification Engineer to join our Processor Verification Team.
In this role, you will be responsible for verifying the core units of our next-generation processors. You will work closely with the architecture and design teams to ensure functional correctness through advanced verification methodologies, taking ownership of verification environments from planning to coverage closure.
Requirements:
Education: B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering.
Experience: 7+ years of hands-on VLSI verification experience.
Core Expertise: Deep knowledge of SystemVerilog and UVM (Universal Verification Methodology).
Skills
Technical Advantages:
o Experience in Processors Verification (arithmetic units, control logic) is a significant advantage.
o Background in RTL Design or a strong ability to read and analyze Verilog implementation.
o Experience with C/C++ programming is an advantage.
o Scripting capabilities (Python/Perl) for automation and flow efficiency.
Personal Attributes:
o Strong Technical Background: You have a solid grasp of logic design principles and problem-solving.
o Independent: Capable of self-learning and driving tasks to completion.
o Creative: Ability to think creatively to find complex bugs and edge cases.
o Collaborative: Excellent interpersonal skills and a team-oriented mindset.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo
Job Type: Full Time
as a cpu design Verification engineer, you will work as part of a research and development team building verification components, constrained-random testing, system testing, and verification closure.
as part of our server chip design team, you will verify complex digital designs. you will collaborate with design and Verification engineers in active projects and perform verification. you will be responsible for the full lifecycle of verification which can range from verification planning, TEST execution, or collecting and closing coverage.behind everything our users see online is the architecture built by the technical infrastructure team to keep it running. from developing and maintaining our data centers to building the next generation of google platforms, we make product portfolio possible. we're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. we keep our networks up and running, ensuring our users have the best and fastest experience possible.
responsibilities
plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
create and enhance constrained-random verification environments using systemverilog or formally verify designs with systemverilog assertions (sva) and industry leading formal tools.
identify and write all types of coverage measures for stimulus and corner-cases.
debug tests with design engineers to deliver functionally correct design blocks.
apply close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, or a related field, or equivalent practical experience.
experience creating and using verification components and environments in standard verification methodology.
experience verifying digital logic at register transfer level (rtl) level using systemverilog or Specman /e for field programmable gate arrays or asics.
preferred qualifications:
masters degree in electrical engineering or Computer Science.
experience with universal verification methodology (uvm), systemverilog, or other scripting languages (e.g., Python, PERL, shell, bash, etc.).
experience with cpu implementation, assembly language, or compute socs.
This position is open to all candidates.
 
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26/03/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
looking for outstanding chip design Verification engineers to join our networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
what you will be doing:
work in a combined design and verification team which develops core units within the networking silicon.
build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
work closely with multiple teams within organizations such as architecture, micro- architecture, full-chip, fw and post-silicon validation.
your daily work will involve all aspects of design verification: planning, coding, coverage and integration
Requirements:
what we need to see:
b.sc or above in electrical engineering or computer engineering, graduation with high scores.
5+ years of validated experience in chip design dynamic verification.
professional verification experience, knowledge in advanced verification methodologies and tools.
demonstrates deep understanding in design and verification logic.
strong debugging, problem-solving and analytical skills.
a great teammate with strong communication and interpersonal skills.
self-motivated, ability to work independently and drive tasks to completion.
ways to stand out from the crowd:
experience in developing verification environments in Specman.
prior design or verification experience of high-speed interconnects and/or SOC.
knowledge in network flows and protocols.
This position is open to all candidates.
 
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26/03/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
we are now looking for a formal verification manager to join our networking team!
as a formal verification manager in networking business unit, you will lead a team of highly skilled formal engineers responsible for verifying the next generation of cutting-edge network products and gpu technologies.
this is a unique opportunity to make a real impact at the heart of ai and hpc revolution, while working in a fast-paced, innovative environment.
you will be part of a passionate and experienced team using leading formal verification tools and methodologies to ensure design correctness at the highest level. your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and Storage applications.
what youll be doing:
lead and grow a team of formal Verification engineers focused on pre-silicon formal verification of complex digital designs.
define and drive formal verification strategies and methodologies to prove the correctness of designs across multiple projects.
collaborate closely with architecture, design, dv teams to identify verification needs and drive closure.
provide technical guidance, mentoring, and support to engineers in the team.
own the planning and execution of formal verification deliverables to ensure high quality and timely tapeouts.
Requirements:
bsc or msc in electrical/computer engineering, Computer Science, or mathematics.
5+ years of managerial experience in a chip design or verification domain.
8+ years of overall industry experience in formal verification, functional verification, or rtl design.
deep understanding of formal verification concepts, tools, and flows.
excellent leadership, problem-solving, and communication skills.
strong analytical and debugging abilities.
ways to stand out from the crowd:
hands-on experience with formal verification
background in developing formal testbenches, assertions, and coverage models.
managerial experience in chip design domain
a passion for recruiting, leading, mentoring engineers and building strong, collaborative teams.
This position is open to all candidates.
 
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26/03/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
we are looking for a senior chip design Verification engineer for developing the next generation dft technologies.
as a senior chip design Verification engineer in the dft team , you will verify the design and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and complex products. our dft solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for verification of the dft design, architecture and micro-architecture using sophisticated verification methodologies.
as a member of our dft verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (testbenches, bfms, checkers, monitors), execute TEST /coverage plans, and verify the correctness of the design.
collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.
Requirements:
what we need to see:
bsc. in electrical engineering or computer engineering, or equivalent experience.
5+ years of practical verification experience.
experience in developing verification environments and random based verification for unit level and system level using verification tools (simulation tools, verilog, debug tools like simvision/debussy).
experience with Specman is a plus.
good understanding of rtl design (verilog).
strong debugging, problem solving and analytical skills.
excellent communication and social skills.
ability to work in a geographically diverse team environment.
self motivated, independent and target oriented.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
in this role, you will work as part of a research and development team. you will build verification components, constrained-random testing, system testing, and drive verification closure. you will verify digital designs, collaborate closely with design and Verification engineers on projects, and perform direct verification. you will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. you will manage the full life-cycle of verification, which can range from verification planning, TEST execution, to collecting and closing coverage.the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
create and enhance constrained-random verification environments using systemverilog and uvm, or formally verify designs with sva and industry leading formal tools.
identify and write all types of coverage measures for corner-cases.
debug tests with design engineers to deliver functionally correct design blocks.
close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering or equivalent practical experience.
8 years of experience with creating and using verification components and environments in standard verification methodology.
experience verifying digital logic at rtl level using systemverilog or Specman /e for fpgas or asics.
preferred qualifications:
master's degree or phd in electrical engineering, or a related field.
3 years of experience with creating and using verification components and environments in standard verification methodology.
experience with verification techniques, and the full verification life cycle.
experience with performance verification of asics and asic components.
experience with application-specific integrated circuit (asic) standard interfaces and memory system architecture.
experience in four or more system on a chip ( SOC ) cycles.
This position is open to all candidates.
 
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26/03/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
we have been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. its a unique legacy of innovation thats fueled by great technology-and amazing people. today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world.
the complexity of the chip has greatly increased over the years. we are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. thesystem -on-chip ( SOC ) group is seeking a top SOC Verification engineer to verify the design and implementation of the worlds leading networking socs. in this position, you will get the opportunity to craft complex networking chips and interact directly with architects, designers, and software engineers across sites. this is your chance to shape the future of computing with a world-class team! as an SOC Verification engineer, you will verify the design and implementation of our SOC technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches and nic SOC product lines. we are working closely with a wide range of aspects - chip design, dft, backend, verification and production testing. we are working on the most advanced technologies and complex products. our SOC solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for verification of the clock design elements, architecture and micro-architecture using sophisticated verification methodologies.
as a member of our SOC verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (testbenches, bfms, checkers, monitors), execute TEST /coverage plans, and verify the correctness of the design.
collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.
Requirements:
bsc. in electrical engineering or computer engineering.
2+ years of relevant experience.
good understanding of rtl design (verilog)
experience of uvm methodology.
strong debugging, problem solving and analytical skills.
excellent communication and social skills.
ability to work in a geographically diverse team environment.
self motivated, independent and target oriented.
way to stand out from the crowd:
previous experience in SOC and/or verification
experience in developing verification environments and random based verification for unit level and system level using verification tools (simulation tools, verilog, debug tools like simvision/debussy)
background with sv/uvm and Python
This position is open to all candidates.
 
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26/03/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? our design-for- TEST engineering team works on groundbreaking innovations involving crafting creative solutions for dft architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. we are looking for a dft engineer to join the atpg team. the position includes taking part in development of the next generation dft technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
working on the most advanced technologies and complex products, our dft solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
Requirements:
you will be in charge of state of the art design for TEST /atpg flows and implementation
take atpg ownership on different dft aspects of a project, arch & planning, pattern generation, verification and post silicon bring up and diagnosis.
inventing and maintaining automation flows that provide the short TEST time to production
what we need to see:
b.sc. in electrical engineering or computer engineering or equivalent experience
5+ years of hands on dft/atpg knowledge & technical experience in dft asic design and in atpg tools
strong programming skills in scripting languages
quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility
ways to stand out from the crowd:
knowledge of dft including scan, mbist, lbist, on-chip scan compression, fault models, atpg, and fault simulation
experience in mentor testkompress atpg tool and retargeting flow
programming languages: tcl, prl, phyton & Unix shell scripts
experience with ate and silicon bring-up
This position is open to all candidates.
 
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26/03/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? our engineering team works on groundbreaking innovations involving crafting creative solutions for dft architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. we are looking for an experienced dft engineer to join the atpg team. the position includes taking part in development of the next generation dft technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
 
working on the most advanced technologies and complex products, our dft solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
 
what youll be doing:
you will be in charge of state of the art design for TEST /atpg flows and implementation
take full atpg ownership end to end on a project, from arch & planning to pattern generation, verification and post silicon bring up and diagnosis.
inventing and maintaining automation flows that provide the short TEST time to production
Requirements:
5+ years of hands on dft/atpg experience knowledge & technical experience in dft asic design and in atpg tools
strong programming skills in scripting languages
bsc. in electrical engineering or computer engineering
quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility
 
ways to stand out from the crowd:
knowledge of dft including scan, bist, on-chip scan compression, fault models, atpg, and fault simulation
experience in mentor testkompress atpg tool and retargeting flow
programming languages: tcl, prl, phyton & Unix shell scripts
experience with ate and silicon bring-up
 
This position is open to all candidates.
 
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26/03/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
we are now looking for a senior verification manager for our fc switch silicon team. as a fullchip verification manager in networking business unit, you'll lead a group of passionate engineers to design and implement the next generation state-of-the-art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
work in a fc team, responsible to integrate and verify the switch at system level
lead and grow a team of fullchip Verification engineers
responsible to drive the fullchip verification execution, including staging plan of the projects and deliveries
provide technical guidance, mentoring, and support to engineers in the team.
work closely with multiple teams within organizations such as architecture, u-arch, full chip micro-architecture, be, and fw
dynamic verification environments planning for units infrastructures and system level
work with design/verification team which develops core units within the switch silicon.
Requirements:
what we need to see:
electrical engineering b.sc. or computer engineering b.sc. graduate with high scores or equivalent experience.
4+ years of managerial experience in a chip design or verification domain.
10+ overall years of experience in rtl design/dynamic verification.
knowledge in network protocols and/or hpc and distributed calculations - advantage.
a team player with good communication and interpersonal skills.
nvidia is widely considered to be one of the technology worlds most desirable employers. we have some of the most forward-thinking and hardworking people in the world working for us. are you creative and autonomous? do you love the challenge of crafting the highest performance & lowest power silicon possible? if so, we want to hear from you. come, join our switch silicon design team and help us build the next chip in this exciting and quickly growing field.
This position is open to all candidates.
 
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