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As a Technical Leader, you will be at the forefront of advancing Tetragons capabilities. You will guide architectural direction while staying deeply engaged in building the systems that power our platform. Your impact will span designing high-performance data pipelines, optimizing database and distributed system performance, and ensuring massive streams of system events can be ingested, aggregated, and distilled into meaningful intelligence.

You will collaborate closely with teams across Cisco, including Hypershield and Splunk, to create the integration points that transform raw data into actionable insights for enterprise security. In this role, youll solve some of the most complex system-level challenges in observability and infrastructure, helping Tetragon evolve to meet the needs of modern cloud-native environments.





What youll do:

Develop high-quality Go (and eBPF) code for the Tetragon project.

Design and implement new Tetragon features to enhance its capabilities for Runtime security detection and enforcement

Design and optimize systems for large-scale Tetragon deployment and operation in K8s or VM platforms

Architect infrastructure that converts raw event data into intelligence streams with minimal performance overhead.

Contribute to open-source projects and represent Cisco Isovalent in community discussions.

Participate in architecture reviews, code reviews, and documentation.

The Design for Test (DFT) team is part of the design group, which focuses on logic design, RTL development, and running verification tests.

Their main role is to design test structures embedded within the chip to ensure proper functionality after manufacturing.

The goal is to detect potential manufacturing defects with maximum efficiency and filter out faulty units before they reach the market.



What You'll Do

Insert DFT logic, perform synthesis, and run Automatic Test Pattern Generation (ATPG) to ensure hardware testability.

Execute Gate Level Simulations, timing checks, and DRC checks to maintain rigorous design integrity and performance standards.

Run regressions and perform deep-dive debugging on simulation failures as part of the core verification process.

Work in a small, agile team with an intimate atmosphere that offers direct mentoring and broad professional growth.

As the Physical Design Manager, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

we are looking for a ASIC Engineer
Your Impact
Review micro-architecture specifications
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab

we are seeking a Physical Design Technical Leader.

About Cardo Cardo Systems is a provider of cutting-edge communication and connectivity devices and applications for powersports and outdoor enthusiasts. In 2026, Cardo is proudly unveiling its Beyond Helmet line, the first of its kind in the motorcycle industry, fostering a new age in safety, sound, and communications. After pioneering the world’s first Bluetooth-based wireless intercom headset in 2004, Cardo has been responsible for many of the industry’s innovations, revolutionizing communication, pushing technological boundaries, and enhancing user safety. Now sold in over 100 countries, Cardo is proud to be the world’s leading communication device for groups in motion. ?Cardo Systems is looking for a Junior Hardware Engineer to join our ATE team and play a key role in the design, development, and integration of advanced test equipment for our cutting-edge multidisciplinary products. In this role, you will be involved in hardware board design, validation, testing, and production support while working across a wide range of technologies including analog, digital, audio, RF, and optical systems. You will collaborate closely with Hardware, Firmware, Manufacturing, and Quality teams to ensure reliable and efficient testing solutions throughout the product lifecycle. Responsibilities:
* Design and develop ATE (Automated Test Equipment) hardware boards and test systems.
* Integrate and validate multidisciplinary technologies including analog, digital, audio, RF, optics, and power circuits.
* Work with microcontrollers and embedded hardware platforms.
* Develop test specifications, test methodologies, and validation procedures.
* Support production activities, troubleshooting, and continuous improvement of manufacturing test processes.
* Perform hardware bring-up, debugging, and characterization using lab equipment.
* Collaborate with cross-functional teams throughout development and production stages.
* Operate effectively in an AI-driven engineering environment.

As a Technical Leader, youll help build the next-generation platform that brings product portfolio together through an AI-native experience. Youll provide hands-on technical leadership to a growing engineering team in TLV while collaborating with global Cisco teams.

Own the technical direction, architecture, and delivery of end-to-end product capabilities.
Translate product goals into scalable designs and executable engineering plans.
Design reliable distributed systems using relational and NoSQL databases, queues, and event-driven architectures.
Build high-quality, modern web experiences and supporting backend services.
Collaborate with architects, product managers, designers, and global engineering teams on cross-product integrations.
Drive security, scalability, resilience, performance, and observability.
Contribute to the codebase, review PRs, and promote engineering excellence.
Mentor engineers and help build a high-performing team.

Review micro-architecture specifications

Supervise verification team members and provide professional guidance

Implement Verification environment UVM based

Collaborate with Design engineers to resolve bugs and achieve coverage closure

Work with the firmware/Lab teams to verify chip flows

Perform debug, root-cause analysis, and post-silicon validation in the lab

we are looking for a C++ Software Engineer
Your Impact

Craft and develop software driving the world's most complex infrastructures

Gain intimate knowledge of world-class silicon and programming models

Work with architecture and design teams to define the next generation of ASIC products being developed

Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the Cisco SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.

Your Impact
Lead and drive DFT verification activities within the Cisco SiliconOne DFT team.

Develop verification plans, environments, checkers, assertions, and coverage models for DFT features.

Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams.

Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features.

Debug complex pre-silicon issues across RTL, verification environments, and DFT logic.

Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV.

Help bridge between general DV methodologies and DFT-specific design and verification needs.

As a Project Manager, you will support multiple ASIC development programs by coordinating execution, tracking deliverables, and enabling collaboration across engineering teams. You will strengthen operational excellence through AI-based automation and tracking solutions. Your work will help teams identify risks and dependencies early, maintain alignment, and deliver programs successfully.

Support Program Managers throughout each phase of ASIC program execution.
Track milestones, action items, dependencies, risks, deliverables, status reports, dashboards, and execution metrics across multiple projects.
Coordinate activities among ASIC, Software, and Business Operations teams, including global stakeholders.
Drive follow-up and accountability to ensure project actions are completed on time.
Develop AI-powered tracking tools and automation solutions that improve project visibility, streamline processes, and strengthen program management methodologies.
Collaborate with engineering and operations teams to maintain alignment and support successful program delivery.

We're looking for a hands-on Software Developer to join our R&D team, working on the full pipeline - cameras, video processing, automated production, graphics, and backend infrastructure. If you love low-level systems, real-time challenges, and seeing your code live in actual sports arenas, this is the role for you.
As part of your role, you will:
Develop and maintain high-performance C++ systems across the video pipeline
Work on real-time video processing, ingest/transcode pipelines, and streaming infrastructure
Collaborate with the team on backend services written in Python and Go
Identify and resolve performance bottlenecks in multithreaded, low-latency systems
Work closely with Product, QA, and DevOps to ship reliable, scalable features
Leverage AI tools (primarily Claude) as part of your daily development workflow

Review micro-architecture specifications
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab