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This role sits at the intersection of AI and high-performance systems engineering, focused on solving real-world problems under strict constraints. You will work on systems where performance and reliability are critical and where improvements have a direct, measurable impact on real-world safety.

This is a senior, systems-focused role with end-to-end ownership over performance and reliability of production computer vision pipelines. You will define optimization strategies, identify bottlenecks across the system, and drive improvements under real-world constraints.

What youll do
Build and optimize real-time computer vision pipelines running on edge systems processing live maritime video streams (e.g, NVIDIA Jetson, Triton Inference Server).
Take models from research and turn them into production-ready, reliable components deployed on vessels.
Profile and improve end-to-end system performance across: multi-camera video ingestion; preprocessing; inference; postprocessing.
Identify and resolve bottlenecks across CPU, GPU, memory, and pipeline coordination.
Make and justify tradeoffs between latency, accuracy, stability, and resource utilization.
Design and implement robust data and inference pipelines (video -> model -> actionable output for crew).
Develop benchmarking and evaluation workflows to measure performance end-to-end and support release gating.
Build and improve observability tools, including logging, monitoring, and debugging workflows for production systems.
Define and maintain clear interfaces between research code and production systems.
Work closely with research and backend teams to integrate new models into production systems.
Continuously improve system efficiency and reliability under hardware and runtime constraints.

Required RTL Design Technical Lead, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use the ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead the Design Activities at IPs, SubSystems(S.S) and SoC.
Plan, execute, track progress, assure quality, report status of the assigned activity.
Lead a team of designers both directly and in teams.
Define the Block/SoC level design documents such as Micro Architectural Specifications.
Own IP, S, SoC strategies for clocks, resets, and debugs. Enforce global methodologies and drive enhancements.

We are looking for a Senior Automation QA Engineer (AQA) to join a team delivering mission-critical systems for a leading financial institution. You will own test automation end-to-end across a layered banking architecture, building the frameworks, suites, and pipelines that keep quality high in a secure, highly regulated environment.
This is a hands-on senior role for an engineer who treats test code with the same rigor as production code. You will define automation strategy, drive coverage across UI, API, and integration layers, and embed automated quality gates into the delivery process. We build with modern, AI-assisted workflows, so QA engineers who are fluent with tools like Cursor and Claude Code will feel at home.
Architecture You Will Test
You will design and maintain automated coverage across all tiers of a layered banking architecture, validating behavior and data flow as it moves through each layer:
Client (React) → BFF (Next.js / JavaScript) → Middleware (.NET / C#) → Core Banking
Key Responsibilities
Design, build, and maintain automated test frameworks and suites across UI, API, and service/integration layers.
Automate end-to-end UI tests for the React client and BFF, and API/contract tests for the .NET middleware and core integrations.
Build, maintain, and optimize automated test pipelines in CI/CD, and embed quality gates into the build and release process.
Define test strategy, test plans, and coverage; partner with developers on where unit, integration, and end-to-end tests belong.
Validate asynchronous and event-driven flows (e.g. RabbitMQ / Kafka) and verify data integrity across services and databases.
Triage failures, perform root-cause analysis, log and track defects, and report on quality metrics and release readiness.
Work within the bank's SDLC and governance - change management, environment promotion, and compliance gates.
Mentor team members on automation best practices and raise the overall quality bar.

we are looking for a Lead SoC Architect
Responsibilities

Definition and detailed hardware specifications of subsystems in the SoC

Breaking down the sub-system architecture into microarchitectural blocks with the related firmware, and SW components.

Understanding the system in which the SoC is integrated to and designing the SoC to perfectly fit into the datacenter system.

We are hiring a Senior Robotics Software Engineer to build the system the autonomy runs inside. You own the runtime - ROS2 architecture, module lifecycle, orchestration, state management, configuration, fault handling, and both ends of the stack: World Model ingestion and the Vehicle Interface down to the platform control systems.

You will face hard real-time constraints, embedded compute, and a system that has to keep behaving correctly when parts of it do not. You own the stack across its full depth, from the interfaces at its edges to how the whole thing behaves in the water.

What Will You Do?
Own the autonomy runtime: ROS2 and modern C++ architecture, module lifecycle, orchestration, state management, data flow, configuration, fault handling and recovery
Implement the system's two contracts: World Model ingestion and Vehicle Interface adapters to the platform control systems
Own deployment to the vessel compute: builds, packaging, versioning, configuration management and CI
Work with system engineering and field teams on vessel bring-up, sea trials and debugging in the field
Build logging, recording, replay and observability - the ability to take any run at sea and reproduce it exactly on a desk
Integrate and operate the simulation environment (SIL)
Own reliability, timing and performance of the stack on embedded hardware

Required Senior CAD Infra Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Work with partner teams to provide the compute, storage, and methodology needs of the chip design, verification, and physical design teams. Collaborate with Application-Specific Integrated Circuit (ASIC) teams to implement tools and methodologies.
Design and implement CAD tools, solutions, and methodologies for ASIC development. Extend the capabilities of third-party tools through their dedicated APIs.
Propose, design, and implement software automation that directly addresses bottlenecks in today's ASIC and SoC EDA flow. Lead and actively contribute to the automation and integration of physical design (floorplanning, power planning, synthesis, place and route, clock tree synthesis, timing closure, STA, DRC, LVS, DFM, etc.) in our automated flow.
Leverage your software expertise to develop the hardware automations required for physical design automation, and their software integration in our automated flow.

We are looking for highly motivated engineers who love the challenges and the opportunity of a small company. Join us and be a part of a small and dynamic team, which revolutionizes the parallel processor architecture.

We are looking for highly motivated engineers who love the challenges and the opportunity of a small company. Join us and be a part of a small and dynamic team, which revolutionizes the parallel processor architecture.

Required Senior Edge-AI SoC Formal Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Pioneer and refine formal verification methodologies by systematically embedding AI tools to optimize verification accuracy.
Plan the formal verification strategy and create the properties and constraints for complex digital design blocks.
Utilize formal property verification tools combined with formal verification closure techniques to verify properties and apply sign-off to blocks.
Architect and implement reusable formal verification components.

We are hiring a Senior Robotics Algorithm Engineer to own the algorithmic core of our unmanned surface vessel: everything between a world state and a safe navigation command. Localization, route and path generation, continuous replanning, encounter reasoning, collision avoidance, COLREG-aware behavior and the decision logic that ties them together are yours. The maritime environment is unforgiving and only partly observable. Other vessels do not declare their intent, tracks are noisy, the sea moves under you, and the rules of the road are written for humans exercising judgment.

You will own the algorithmic core end to end. From the moment a world model arrives to the moment the vessel commits to a maneuver, every navigation decision the system makes is one you designed.

What Will You Do?
Own the algorithmic path from world state to safe navigation commands, end to end.
Design and implement global and local planning: route generation, waypoint generation, path following, and continuous replanning as conditions change.
Build collision avoidance for dynamic maritime environments: encounter detection and classification, reasoning about other vessels' course, speed, intent and uncertainty, maneuver selection and timing, and return-to-route logic.
Design mission-level decision logic: continue, deviate, hold, abort, transition to safe state and define the behavior envelope.
Build the data pipeline and own performance in simulation and at sea.

We are hiring a Principal Autonomy Engineer to architect and lead the autonomous navigation stack of our unmanned surface vessel. You will own the architecture end to end - World Model, planning, decision making, vehicle interface, and you will decide how the brain itself is built: module decomposition, behavior architecture, arbitration, state ownership, and the core technology choices behind them. You will define technical requirements and reference scenarios, own the safety and degradation architecture, and hold the interfaces between autonomy, perception, the vessel platform and the field teams.

This is not an architecture role away from the code, but it is a leadership role. You will set the technical direction of the group and you will write the parts that matter most yourself - hands on principal.

What Will You Do?
Own the end-to-end architecture of the autonomous navigation stack: World Model - Planning - Decision Making - Vehicle Interface.
Define and own the World Model Contract: representation, uncertainty, timing and synchronization, coordinate frames, confidence and degradation modes.
Define and own the Vehicle Interface Contract: command semantics, platform guarantees, latency and failure behavior, and the abstraction that keeps the stack portable across platforms.
Decide how the autonomy brain is structured - module decomposition, behavior architecture, arbitration between behaviors, state ownership, data flow.
Design the safety and fail-safe architecture: degradation ladder, safe-state transitions, operator intervention, fault containment.
Stay hands-on in planning and decision-making code where the hardest problems are.
Lead technical hiring and technical direction for the autonomy group as it grows.

we are looking for a Senior SW Engineer [Codegen]
Job Description

Join a multi-disciplinary team of experts operating at the core of Speedatas software stack

Lead the design and implementation of highly efficient algorithms that maximize our performance

Develop time-critical Python components that translate database operations to performant, hardware-optimized C++

Co-design the next generation of our architecture alongside Hardware & Software engineering leads

Research state-of-the-art algorithms and techniques for data analytics and hardware acceleration

Fly high with the SW, and dive in for a byte of the HW

Required Power and Signal Integrity Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
You'll set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners.
The ML, Systems, & Cloud AI (MSCA) organization designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all services (Search, YouTube, etc.) and Cloud.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities:
Design and optimize power distribution networks (PDN) across chip, package, and board levels. This includes managing power/ground planes, decoupling capacitors, and power gating strategies.
Conduct both pre-layout and post-layout power integrity simulations to analyze power and ground noise (SSN/SSO), voltage drops (IR drop), and electromagnetic interference (EMI).
Implement and verify low-power design methodologies, such as multi-voltage designs and clock gating, using power intent formats like UPF/CPF.
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR), Spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.

Required Senior Edge-AI SoC Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
We're the driving force behind groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

We're looking for a hands-on systems engineer to lead prototyping and low-volume assembly (tens to hundreds of units) - taking hardware from first builds to a repeatable process, designed with scale-up and BOM cost in mind.

Responsibilities
Lead prototype and pilot builds; turn lessons into a repeatable assembly process.
Plan assembly flows, fixtures/jigs, and the right (minimal) automation - engineering simplicity first.
Own the project plan (Gantt) and budget; design for scale-up with BOM cost awareness and DFM feedback to R&D.
Define test and inspection strategy, including environmental testing where needed.
Measure and improve yield and rework with data; work daily with R&D, production, and vendors on the floor.