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We are seeking an AI Networking Architect to join the Networking Research Group. This role bridges the gap between emerging AI workloads and the data center infrastructure that powers them, working at the intersection of AI applications, distributed systems, networking hardware, and software architecture. You will join a focused team of multidisciplinary engineers driving AI workload optimization through deep application understanding, network analysis, and end-to-end systems thinking. Your insights will directly shape our products across the full stack - from applications and software libraries to hardware architecture and physical design.


What you'll be doing:
Model the performance of complex AI workloads to identify bottlenecks and recommend system-level optimizations.
Analyze new AI models, distributed training techniques, and inference workloads to understand their infrastructure requirements.
Build simulation and hardware platforms, run real AI workloads on them, and develop analytical tools to evaluate trade-offs across compute, memory, storage, and network behavior.
Translate research insights and workload behavior into actionable software, xhardware, and networking architecture requirements.
Partner with architecture, software, and product teams to influence our future networking and AI infrastructure roadmaps.
Drive architectural innovation by applying deep workload analysis to production machine learning frameworks.

We are is looking for a strong technical senior architect to join us in shaping the future. Senior Architects are innovators who can translate business needs into workable technology solutions. Their expertise is deep and broad. They are hands on, producing both detailed technical work and high-level architectural designs.

As a Senior architect in the AI Networking Research team, you will explore technological challenges on accelerate networking and building AI data centers. Research new transport functions and semantics for optimizing AI workloads, AI systems communication and accelerations and much more. You will also be leading architectural and development efforts across numerous technological fields, related to the modern AI data center, such as distributed AI and deep learning solutions, data analytics, High Performance Computing (HPC), Software Defined Networking (SDN), virtualization, storage, and more.

What youll be doing:

Enhance our GPU Networking offerings for accelerating AI workloads, such as our Dynamo, our NIXL and our UCX, tailored to the unique requirements of AI workloads.

Co-design hardware features (e.g., in GPUs, DPUs, or interconnects) that accelerate data movement and enable new capabilities for inference and model serving.

Identify and evaluate new technologies, innovations and partner relationships for alignment with our technology roadmap and business value.

Lead architecture and design of new technologies and innovations such as runtime systems, communication libraries, AI-specific technologies.

Lead proof-of-concept development to evaluate and drive such technologies.

We are looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing our groundbreaking and innovative chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:

Join the Tel Aviv or Beer-Sheva group, working on RiscV processors platform.

Verification for chip blocks according to specifications under challenging constraints and with high orientation to power, area and performance.

Daily work might involve any or all aspects of chip development including verification, integration, debug

Work closely with firmware and other groups around the globe.

BIRD Aerosystems is a global leader in the development of advanced airborne defense, intelligence, and surveillance solutions for military, governmental, and commercial aviation. Our innovative technologies are deployed worldwide, supporting mission-critical operations and protecting aircraft through advanced multidisciplinary systems. As we continue to grow, we are looking for a talented Hardware Design Engineer (Board Design) to join our Hardware Development team and contribute to the design and development of advanced electronic boards for complex aerospace and defense systems. What You’ll Do · Design, develop, and modify electronic boards throughout the entire product lifecycle. · Perform board bring-up activities following development and initial manufacturing. · Troubleshoot hardware issues, analyze failures, and implement design improvements. · Edit schematics and support PCB layout activities. · Improve product manufacturability and maintain production documentation. · Support PCB manufacturers and electronic assembly subcontractors while ensuring compliance with IPC standards. · Investigate manufacturing failures and provide engineering solutions. · Work closely with multidisciplinary teams including Mechanical, Software, Firmware, and System Engineering. · Participate in design reviews (PDR/CDR). · Prepare engineering documentation, test procedures, and product verification documents. Support the transition from development to production.

We are looking for a Chip Design micro architect for the Networking Silicon group. As a chip micro architect in our Networking business unit, you will join a group of passionate engineers to implement the next generation state-of-the-art BlueField DPU SOC and/or ConnectX NIC that deliver breakthrough networking, security, cloud, AI and storage performance to the AI data centers. As a design micro architect, you will make a real impact in a dynamic, technology-focused AI company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:
You will be part of a small and exclusive micro-architecture team and have the opportunity to make a real impact in designing the micro-architecture of the next generation state of the art network card hand in hand with the product architect making sure implementation meets the product goals.
Work closely with architecture and design teams to thoroughly understand system requirements and identify micro-architecture solutions, while weighing trade-offs related to performance, area and power consumption.
Break high-level arch requirements into lower-level design building blocks. Focal point for the design team, reviewing implementation and guiding the team.
Find bottlenecks early in the development cycle using performance analysis and simulations.
Use your understanding of the entire chip and system to identify and debug pre and post silicon full-chip issues.

We are seeking a passionate QA Engineer to join our FW testing team. This position will be part of our growing team, helping NVIDIA products meet industry-leading benchmarks for efficiency and quality. As a Firmware QA Engineer, you will be immersed in the latest advancements and actively contribute to developing world-class products. Your efforts will directly impact the performance and quality of our offerings, ensuring they consistently meet industry-leading standards.


We are looking for ideal candidates who will actively test industry-leading features in the FW sector, quickly learn new features, conduct both manual and automated testing, and contribute to the development of automation systems.


What you'll be doing:
Review arch design and requirements documents for new features introduced in the Nvlink program.
Join the effort of QA shift left towards simulation for NVL7 generation.
Design, develop, and perform tests for the new features, as part of FW GA or update releases.
Automate newly added tests in the existing automation framework, and add new capabilities and features to the framework.
Report bugs found during execution, assist with reproduction and debugs to understand root cause, verify bug fixes provided by R&D team, and raise if not fixed.
Fully collaborate with different external teams like : :product marketing, R&D, and verification.
Define and build setups topologies for appropriate product coverage.

The Networking Diagnostics team is seeking a highly motivated and experienced engineer. This person must have hands-on technical expertise to develop critical diagnostic tools for our newest, world-leading networking platforms. This position offers the opportunity to have a real impact in a dynamic, technology-focused company, impacting data centers and high-performance computing (HPC) clusters across the world. We are looking for independent engineers who excel in a fast-paced environment and are passionate about ensuring the stability of next-generation hardware.

What you'll be doing:
Design & Implement: Architect and develop high-performance diagnostic tools and frameworks using Python, tailored for our latest networking platforms.
Performance Optimization: Drive end-to-end development focusing on software that performs efficiently, ensuring diagnostic suites can handle high-throughput data and real-time monitoring without latency.
System Diagnostics: Take charge of developing features that bridge the gap between complex hardware behaviors and software-level diagnostics.
Collaborative Problem Solving: Partner with hardware, firmware, and driver teams to address real-world challenges that demand innovative solutions and a customer-centric approach.
Autonomous Execution: Own the full software development lifecycle of diagnostic features, from initial hardware specification to deployment in dynamic environments.

We are looking for a Technical Lead to join our Network System Validation group and lead the validation of advanced networking solutions across complex AI cluster environments. This is a deeply hands-on technical leadership role, combining ownership of the validation roadmap with technical mentoring and engineering excellence. You will develop validation methodologies and automation frameworks, while working hands-on on debugging, performance analysis, and cutting-edge AI networking technologies at scale. Join us to help push our networking technologies to their limits and shape how next-generation AI infrastructure is validated.

What youll be doing:

Review system and product requirements, design validation methodologies, develop and implement comprehensive test plans, functional and performance, for networking technologies in large-scale AI cluster solutions

Develop and maintain benchmarks, automation tools and scripts for test execution, environment setup, log collection, and data analysis.

Lead end-to-end investigation of complex issues by reproducing real-world scenarios, analyzing logs, telemetry, packet captures, and system metrics to identify functional issues and performance bottlenecks, triaging problems across the hardware and software stack, and driving them to root cause and resolution

Read and understand source code (C/C++/Python) to investigate defects, validate fixes, and improve logging, instrumentation, and debugging capabilities

Collaborate deeply with software and hardware development teams to debug networking technologies, including NCCL, RoCE, RDMA, and related software components using targeted experiments and code inspection

Profile and research AI training and inference workloads, correlating application behavior with network and system telemetry to identify scalability and performance limitations

Document findings, communicate technical results, and continuously improve validation methodologies, automation environments, and engineering processes

We are looking for an experienced DFT Design Engineer to join the DFT design team and develop the next generation DFT technologies.

As a design engineer in the DFT design team, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.



What you'll be doing:

In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.

As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.

Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

Our Analog Layout design team is looking for a Senior Analog Layout Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling challenge high-speed mixed-signal circuit designs. We have continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. We are a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our lifes work, to amplify human creativity and intelligence.

What you'll be doing:

Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, SerDes, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS FinFET technologies using Cadence tools.

You will work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.

Job duties will include floor planning, custom layout and verifying against design rules and schematics, EM/IR analysis.

We are looking for a Chip Design Manager to join our Switch Silicon team. As a Chip Design Manager in our Networking Business Unit, you'll join a group of passionate professionals to design and lead the implementation of the next generation of state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!


What You'll Be Doing:

Lead a team of design and verification engineers that develops core units within the Switch Silicon.

Handle micro-architecture for RTL and simulation environment planning for units and modules.

Be responsible for the delivery of complex RTL units and their verification.

Work closely with multiple teams within the organization, such as Architecture, Full Chip, Micro-Architecture, BE, and FW.

Networking unit has continuously reinvented itself over two decades. Our high-speed products are leading in the markets with innovative ways to improve speed and bandwidth from one generation to another. Today, we are increasingly known as the place for getting End-to-End High-Speed Ethernet and InfiniBand Solutions. We're looking to grow our company and build our teams with smart people who can join us at the forefront of technological advancement. Our IC Packaging design team is looking for a Senior IC Packaging Design Engineer to join our package team. and focus on delivering and designing state of the art high-speed Interconnect systems for Supercomputers and Datacenters. This position will collaborate with Technical Package Lead and cooperation with different design teams and development of complex, detailed layout of IC substrates for our products.

What you'll be doing:

As part of a IC Packaging design team, you will collaborate to implement high speed and PDN design for ASIC packages.

Develop symbols, pad stack and perform substrate package routing, placement, stack-up, reference plane, power distribution using Cadence APD (Allegro) or SiP tools.

Optimize package pin out incorporating system level trade-offs of pins assignment.

Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations.

In close co-operation with the SI/PI/HW design teams and product teams.

Planning, ensuring stakeholder management and leading projects from start to finish.

The Senior Silicon Photonics PIC Design Engineer will help build next-generation Photonic Integrated Circuits (PICs) that power high-performance optical interconnect solutions. In this role, you will lead the design, simulation, layout, and system-level testing of advanced silicon photonics components, while contributing to optical test instrumentation for emerging semiconductor test markets.
As a member of the Silicon Photonics Engineering Staff, you will be a key player in the definition, implementation, and validation of complex automated test equipment that interfaces optical ports of silicon photonic devices at all stages of fabrication, from wafer probe to packaged test.
Lead the design, simulation, layout, and system-level testing of advanced silicon photonics components and Photonic Integrated Circuits.
Utilize simulation and design tools, including Ansys/Lumerical and Cadence Virtuoso, to design, validate, and optimize photonic designs.
Collaborate closely with design, layout, EIC, packaging, validation, quality, and system architecture teams to develop high-performance integrated photonic circuits and validate link performance.
Partner with fab and process engineers to define and optimize device design and implement process monitoring structures.
Develop test and qualification plans in coordination with validation and quality engineering teams.
Conduct rigorous testing and characterization of devices and PICs, including passive and active photonic components.
Engage in direct collaboration with silicon foundries to streamline processes and support successful tape-out execution.

The Senior Silicon Photonics PIC Design Engineer will help build next-generation Photonic Integrated Circuits (PICs) that power high-performance optical interconnect solutions. In this role, you will lead the design, simulation, layout, and system-level testing of advanced silicon photonics components, while contributing to optical test instrumentation for emerging semiconductor test markets.
As a member of the Silicon Photonics Engineering Staff, you will be a key player in the definition, implementation, and validation of complex automated test equipment that interfaces optical ports of silicon photonic devices at all stages of fabrication, from wafer probe to packaged test.
Lead the design, simulation, layout, and system-level testing of advanced silicon photonics components and Photonic Integrated Circuits.
Utilize simulation and design tools, including Ansys/Lumerical and Cadence Virtuoso, to design, validate, and optimize photonic designs.
Collaborate closely with design, layout, EIC, packaging, validation, quality, and system architecture teams to develop high-performance integrated photonic circuits and validate link performance.
Partner with fab and process engineers to define and optimize device design and implement process monitoring structures.
Develop test and qualification plans in coordination with validation and quality engineering teams.
Conduct rigorous testing and characterization of devices and PICs, including passive and active photonic components.
Engage in direct collaboration with silicon foundries to streamline processes and support successful tape-out execution.