We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the Cisco SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.
Your Impact
Lead and drive DFT verification activities within the Cisco SiliconOne DFT team.
Develop verification plans, environments, checkers, assertions, and coverage models for DFT features.
Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams.
Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features.
Debug complex pre-silicon issues across RTL, verification environments, and DFT logic.
Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV.
Help bridge between general DV methodologies and DFT-specific design and verification needs.
Requirements: Minimum Qualifications
B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field.
5+ years of experience in design verification roles.
Strong experience with SystemVerilog and UVM-based verification environments.
Experience developing verification plans, coverage models, assertions, and debug flows.
Strong communication skills and ability to work closely with cross-functional teams.
Motivation to learn DFT concepts and become a key contributor in the DFT DV domain.
This position is open to all candidates.