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We are looking for an experienced DFT Design Engineer to join the DFT design team and develop the next generation DFT technologies.

As a design engineer in the DFT design team, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.



What you'll be doing:

In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.

As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.

Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

We are looking for a Mechanical Design Engineer to join our mechanical engineering department as a key player in the development of next-generation high-performance interconnects optical solutions for data center servers and storage systems. This key position includes leading the product design throughout all lifecycle stages from inception to Mass production, close interaction with HW, PMC (Product management & configuration), NPI, Thermal, Layout, Quality, and Supply chain teams.


What youll be doing:

Drive all the mechanical design aspects of optical transceivers, including PCB design, opto-mechanical chain and mechanical envelope.

Independently lead product design from concept, through detailed design, and support it during Qualification, NPI and MP stages.

Collaborate in research of ground-breaking technologies, materials, and processes with other groups to bring in creative ideas that solve ever-growing needs.

our company's product is built around an AI agent that security analysts and detection engineers work with directly. It investigates coverage questions against live enterprise security data, authors and tests detection logic, and tunes noisy alerting.
That agent is already in production with enterprise design partners. Now we need to make it dependable and scalable enough for GA.
You will own that evolution: the agent architecture, its evaluation and quality system, and the production engineering around it. This is a hands-on senior IC role with real architectural authority - you set the technical direction and you write the code.
The agent operates inside customer security environments, where a wrong action can become a customer incident. Correctness, isolation, observability, and evaluation are not polish. They are the product.
What you'll be doing
Agent architecture: Design the evolution from today's production single-agent system to a multi-agent one: orchestration, task decomposition, runtime and framework choices, and a migration path that does not break what design partners already rely on.
Agent capability: Own the prompts, context, skills, and tool design that make the agent genuinely good at detection engineering across multiple security platforms, not just plausible-sounding.
Evaluation platform: Build the harnesses, judges, and golden datasets that turn "the agent feels better" into a number, plus the CI gates that keep regressions from shipping.
Reliability and safety: Keep long-running agentic sessions healthy in production, and build the isolation and guardrails required of an agent working inside enterprise security environments.
Production debugging: Work real failures from production traces, and turn each one into an eval case that can never regress silently.
Technical direction: Make the calls on architecture, sequencing, and quality bar and be accountable for the outcome, including raising how AI-natively the whole team builds.
Cross-team partnership: Partner with product and customer-facing teams on what the agent should do, and with platform teams on the data and integrations it depends on.

We are looking for a Senior Support Engineer to join our Israel-based support team. This role is critical to maintaining excellent service for our English and Hebrew-speaking customers, handling complex technical and customer-facing issues independently, and helping the team adapt to the next generation of AI-enabled support workflows.
The ideal candidate is a strong hands-on problem solver, an excellent communicator in Hebrew and English, and a senior team player who can elevate team quality, partner closely with leadership, and contribute to improving our internal tools, AI-based workflows, and support processes.
This is a hands-on senior individual contributor role with broad impact. In addition to resolving complex customer issues end to end, this person will help shape how support operates in an evolving environment that increasingly includes automation and AI-assisted workflows and tools.
Why this role matters:
Israel is a critical support hub for our business. Some of our customers require high-quality support in Hebrew, especially in complex or sensitive cases where local language, context, and live communication are essential.
At the same time, the support role is becoming more complex. AI-based tools and automation are becoming part of daily work, raising the bar for ownership, judgment, adaptability, and cross-functional collaboration. We need a senior team member who can thrive in this environment, help the team adopt new ways of working, and contribute to improving the tools and processes we use.
What youll do:
Own complex technical and product-related support cases from investigation through resolution.
Provide high-quality support to customers in Hebrew and English across written and live interactions.
Handle ambiguous, high-impact, or cross-functional issues with strong judgment and minimal supervision.
Act as a senior point of contact for escalations, sensitive customer situations, and priority cases.
Mentor teammates by sharing knowledge, setting a high bar for case handling, and helping improve team practices.
Use AI-based tools and internal tools effectively in day-to-day work to improve speed, quality, and consistency.
Help to define, maintain and improve support agents, AI-assisted tools, bots, workflows, automations and documentation to improve support effectiveness.
Identify opportunities to reduce friction, improve self-service, and optimize internal support flows.
Collaborate with Product, R&D, Customer Success, TPE, and other internal stakeholders to resolve issues and improve the customer experience.

We are seeking a highly skilled and versatile Performance Research and Analysis Manager to join our Performance Group. This role will drive end-to-end performance strategy and execution for our next-generation data centers and solutions based on GPU systems, NIC, Switch, DPU and Networking technologies. The ideal candidate will oversee, evaluating, and optimizing end-to-end AI GPU cluster-level performance for scaling out large scale distributed training and inference jobs communication. The role will focus heavily on RDMA, Networking Protocols, Collective Communication, Congestion Control, and Load Balancing algorithms. Secondarily, you will lead our DPUs and Storage technologies for N-S use cases to support AI Inference jobs. Third, you will drive our Performance Dashboards and Observability for cluster-level performance analysis from a stream line telemetry across NICs, Switches, GPUs, and NVlink.

What you'll be doing:

Drive end-to-end performance strategy, characterization, test plans, and optimization for our next-generation AI GPU clusters, focusing on large-scale distributed training and inference workloads.

Deeply evaluate and optimize our Networking core technologies performance, including RDMA/PRDMA, networking protocols, collective communication (NCCL), congestion control, and load-balancing algorithms.

Work on performance research and analysis of our DPUs and storage technologies in North-South (N-S) use cases and deployment scenarios to maximize performance and efficiency for AI inference jobs.

Drive the strategy for performance observability and dashboards across our next-generation data center solutions and supercomputers by leveraging scalable, streamlined telemetry pipelines to build performance dashboards and automated analytics based on real-time performance metrics across NICs, Switches, GPUs, and NVLink boundaries.

Perform deep root-cause analysis (RCA) on complex multi-node performance bottlenecks, driving actionable mitigation plans across hardware, firmware, and software teams.

We are looking for a talented Senior Software infrastructure and tools Engineer to join the Data Processing Unit (DPU) SW Group. As a part of the team, you will lead complicated integrations which combining new technologies, automating processes, bringing up full software stacks, developing system scripts for cutting edge networking technologies with the quality requirements of industry-leading customers. You will work closely with our SDK development and gain an understanding of our products and technologies.

What youll be doing:

Crafting efficiency and usability improvements across our proprietary products that will help streamline various release pipelines and processes across us.

Definition and development of SDKs to be used for DPU SW development.

POC of new technologies that require additional development/integration efforts.

Creating and maintaining build system for complex SW products.

Developing tools using our various proprietary and other cutting-edge technologies.

Collaborate with team members, Architects, design, QA teams, and verification.

Our Analog Layout design team is looking for a Senior Analog Layout Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling challenge high-speed mixed-signal circuit designs. We have continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. We are a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our lifes work, to amplify human creativity and intelligence.

What you'll be doing:

Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, SerDes, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS FinFET technologies using Cadence tools.

You will work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.

Job duties will include floor planning, custom layout and verifying against design rules and schematics, EM/IR analysis.

we are building an AI-powered reverse engineering agent. As a Frontend Engineer, youll build high-signal interfaces for expert users, security researchers working inside complex binaries and large codebases.
This role is about developer tooling and research productivity, not marketing pages. Youll turn complex analysis outputs into interfaces that are fast, precise, and genuinely useful.
What Youll Do
Build UI for reverse engineering and research workflows
Partner with backend and research teams to surface complex insights clearly
Design and implement interfaces for navigating large, messy codebases
Improve performance, usability, and clarity for expert workflows
Own frontend features end-to-end: from spec → implementation → polish.

We are looking for a Chip Design Manager to join our Switch Silicon team. As a Chip Design Manager in our Networking Business Unit, you'll join a group of passionate professionals to design and lead the implementation of the next generation of state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!


What You'll Be Doing:

Lead a team of design and verification engineers that develops core units within the Switch Silicon.

Handle micro-architecture for RTL and simulation environment planning for units and modules.

Be responsible for the delivery of complex RTL units and their verification.

Work closely with multiple teams within the organization, such as Architecture, Full Chip, Micro-Architecture, BE, and FW.

We are looking for an experienced Integrator to join our production line for industrial digital printing machines. This role involves working in a multidisciplinary environment, integrating, maintaining, and troubleshooting advanced printing systems that include mechanical, electrical, electronic, laser, and pneumatic components.

If you have strong technical capabilities, a creative mindset, and the ability to solve problems in real time - we would love to hear from you.

Key Responsibilities

Perform complex integration and assembly processes on industrial digital printing machines within the production line
Troubleshoot and resolve real-time issues across multidisciplinary systems (mechanical, electrical, electronic, pneumatic, and laser)
Disassemble and reassemble components for repair and maintenance purposes
Document failures and write detailed technical reports on troubleshooting processes and implemented solutions
Collaborate with cross-functional teams including Engineering, Quality, and Logistics to improve processes and ensure smooth operations
Use advanced diagnostic tools and technical equipment to identify and resolve system issues

As R&D researcher, you will conduct researches & investigation in variant fields , to develop and shape HP Indigos future platforms.

Responsibility on the printing process development of tomorrow's HP Indigo engines to meet print quality and cost targets

Study and optimize physical process parameters and materials to achieve best in class print quality

Design, perform, analyse and summarize experiments involving multi-disciplinary knowledge. Share findings with relevant stakeholders both in technical community and at management level

Convert marketing requirements into engineering requirements, based on theory and experiments

Develop and improve quantitative measurement methodologies

Develop physical models to characterize systems, interactions between subsystems, understand physical mechanisms and define critical parameters

Working with a diverse group of physicists and engineers helping to solve complex problems.

We are seeking an NPI Engineering Build Manager who is passionate about working on products that enable deep learning. Our team manages the NPI networking supply chain for engineering activities. Activities start from very early engagement with design engineering team and follow through all quick turn NPI builds at the shortest possible cycle time. Our team supports all these engineering quick turn activities by engaging with the engineering team, material suppliers, Operations team, and the PCB manufacturing team. All the parties need to be kept aligned while engineering keeps changing either the material sets or the process.


We are looking for someone can work in a dynamic and fast-changing environment. You are someone who enjoys working on groundbreaking technology and enjoy working with people to take on problems. As a Build Project Manager, you are able to see both the high-level view and be proficient in tracking and following up on detail whether it is an existing product that requires new qualifications or a ground up new product. We will expect you to understand technical detail and be able to translate that into program impact.


What you'll be doing:
Build project's production plan per product's lifecycle, and execute it with NV manufacturers
Communicate with other team members and suppliers to get project details.
Flexibility to adapt to changing requirements, diverse project needs, and tight timelines.
Ability to report on program details in Alignment meetings.
Track and communicate key deliverables, constraints, risks, dependencies and clearly identify critical paths while working with ASIC, product, test, software, board, system engineering and planning teams and other program managers towards a common goal.
Manage cross-functional communications independently, work within a matrixed and publish progress/roadblocks and highlight risks to upper management.
Bring diverse and globally distributed teams together to tackle complex problems and work towards closure.
Lead and attend cross-functional NPI meetings related to your product and highlight key Ops issues while ensuring that the product is ready for production.
Be an active participant in the NPI team by recommending methodology improvements that we can practice as a team.

Networking unit has continuously reinvented itself over two decades. Our high-speed products are leading in the markets with innovative ways to improve speed and bandwidth from one generation to another. Today, we are increasingly known as the place for getting End-to-End High-Speed Ethernet and InfiniBand Solutions. We're looking to grow our company and build our teams with smart people who can join us at the forefront of technological advancement. Our IC Packaging design team is looking for a Senior IC Packaging Design Engineer to join our package team. and focus on delivering and designing state of the art high-speed Interconnect systems for Supercomputers and Datacenters. This position will collaborate with Technical Package Lead and cooperation with different design teams and development of complex, detailed layout of IC substrates for our products.

What you'll be doing:

As part of a IC Packaging design team, you will collaborate to implement high speed and PDN design for ASIC packages.

Develop symbols, pad stack and perform substrate package routing, placement, stack-up, reference plane, power distribution using Cadence APD (Allegro) or SiP tools.

Optimize package pin out incorporating system level trade-offs of pins assignment.

Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations.

In close co-operation with the SI/PI/HW design teams and product teams.

Planning, ensuring stakeholder management and leading projects from start to finish.

The Senior Silicon Photonics PIC Design Engineer will help build next-generation Photonic Integrated Circuits (PICs) that power high-performance optical interconnect solutions. In this role, you will lead the design, simulation, layout, and system-level testing of advanced silicon photonics components, while contributing to optical test instrumentation for emerging semiconductor test markets.
As a member of the Silicon Photonics Engineering Staff, you will be a key player in the definition, implementation, and validation of complex automated test equipment that interfaces optical ports of silicon photonic devices at all stages of fabrication, from wafer probe to packaged test.
Lead the design, simulation, layout, and system-level testing of advanced silicon photonics components and Photonic Integrated Circuits.
Utilize simulation and design tools, including Ansys/Lumerical and Cadence Virtuoso, to design, validate, and optimize photonic designs.
Collaborate closely with design, layout, EIC, packaging, validation, quality, and system architecture teams to develop high-performance integrated photonic circuits and validate link performance.
Partner with fab and process engineers to define and optimize device design and implement process monitoring structures.
Develop test and qualification plans in coordination with validation and quality engineering teams.
Conduct rigorous testing and characterization of devices and PICs, including passive and active photonic components.
Engage in direct collaboration with silicon foundries to streamline processes and support successful tape-out execution.