לוח משרות דרושים מדעים מדוייקים משרה מלאה

An exciting semiconductor startup is seeking an outstanding formal verification
engineer to develop a new type of massively parallel architecture.
This is a rare and exciting opportunity to join an evolving team and company,
allowing you to influence the future of both processor architectures and
database systems.

Job Description
We are looking for highly motivated engineers who love the challenge and the opportunity
of a small company. Join us and be a part of a small and dynamic team, which revolutionizes the parallel processor architecture.

An exciting semiconductor startup is seeking an outstanding verification engineers to develop a new type of massively parallel architecture.

This is a rare and exciting opportunity to join an evolving team and company, allowing you to influence the future of both processor architectures and database systems.

Job Description
​​We are looking for highly motivated Engineers who love the challenge and the opportunity of a growing company. Join us and be a part of a small and dynamic team, which is revolutionizing the parallel processor architecture.

Provide our customers technical and engineering expertise in their ASIC design HW verification process, using our HAV Platforms and Solutions:
Analyze customers verification methodologies and targets, platform and Testbench solutions planning.
Drive and execute HAV products Evaluations on customers designs.
Support customers in deployment of the HAV products, from RTL code compilation and synthesis, towards SoC-level full functionality bring-up on the systems.
Hands-on bring-up of Emulation Testbenches, including interface protocol Transactors, memory models SpeedAdapters, C++ code, and automation scripts.
Regularly interact with customers as their first contact to address any quality issue or required improvements in our products and their collaterals.
Work internally with R&Ds to provide feedbacks on products, track development process and roadmaps.
Work internally with Sales team on accounts strategy and business growth opportunities.

we are seeking for a V&V Engineer, to join the QA, RA & CA department.
As a V&V Engineer, your principal task will be to verify and validate Medical Devices. You will be responsible for HW & System testing including test protocols and reports.
The main responsibilities within this role:
Design, develop and execute system Verification and Validation test procedures.
Responsible for writing detailed, comprehensive, and well-structured V&V test protocols and reports ensuring requirements coverage and traceability.
Analyzing issues and failures in the system.
Work in a highly multidisciplinary and complex technical environment and lead testing of cross-functional projects (with emphasis on mechanical and electro-optical aspects)
Being involved in the reliability and integration tests for prototypes under development
Coordination and management with external testing laboratories
Define and maintain the Verification & Validation plans.
Plan and arrange the work, schedules, and equipment required for testing and evaluating standard and special devices.
Identify, investigate, and document all findings raised during testing.
Work closely with cross functional team members including R&D (System, SW&HW), QA, RA and Product departments.

We are looking for a Senior Chip Design Verification Engineer for developing the next generation DFT technologies.

As a Senior Chip Design Verification Engineer in the DFT team in our coompany, you will verify the design and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our DFT solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.

What you'll be doing:
In this position, you will be responsible for verification of the DFT design, architecture and micro-architecture using sophisticated verification methodologies.
As a member of our DFT verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.
Collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

We are looking for a skilled and driven Experiment Operator to join our team.
As an Experiment Operator, your role will be examining and interpreting extensive datasets in order to derive valuable insights and offer actionable solutions.
You will have the opportunity to work both independently and collaboratively in a variety of testing environments, such as laboratories and outdoor settings.
It is expected that you display proficiency in operating multiple devices efficiently.
Additionally, your contribution will be valuable in creating test plans and reports to effectively manage and organize test data.

Required ASIC Verification Engineer
Verification Group in a growing group responsible for pre-silicon ASIC Verification of complex chips implementing an advanced modem technology.
As part of the role, you will architect, develop & own blocks / sub-subsystem / system-level verification benches. You will be a major contributor to advanced SV UVM methodologies and to infrastructure development. You will be part of an advanced development flow, using state-of-the-art development & Verification tools and will work closely with the chip architects and RTL / VLSI design teams.
RESPONSIBILITIES
The Verification Engineer will be responsible for different HW blocks at module-level and sub-system level and is expected to:
Have an expert-level understanding of assigned HW blocks as well as a good understanding of the block in the context of whole system.
Communicate with architect, designer, algorithm and other verification engineers to lead complex verification tasks, both on module-level and sub-system testing.
Design complete verification environments.
Implement design in full UVM environment.
Perform full block regressions and collection of functional coverage.