דרושים Ready

Requirements:
2+ year of experience with RTL design
Preferably experience in high-speed SERDES (PCIe, Aurora, Ethernet)

Requirements:
- B.Sc./M.Sc. in Electrical Engineering or Computer Engineering
 - 7+ years of hands-on experience in VLSI Verification
 - Strong knowledge of SystemVerilog and UVM
 - Experience with C / C ++ and Python or PERL - advantage
-  Background in RTL analysis and complex logic verification - advantage

Requirements:
- 3+ years of hands-on experience in development using C ++/ C and/or Rust.
- Experience in developing network oriented systems.
- Solid understanding of communication protocols and internet technologies.
- Experience working in a Linux environment, familiarity with operating system internals and Kernel level concepts.
- Strong research and analytical abilities, including independent investigation, analysis of complex data, and translating theoretical concepts into practical, working code.