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The main scope of this role is to lead our silicon debug efforts and provide insights related to complex design issues, open test holes, low yield events and reliability failures, related to our cutting-edge silicon-based products embedded into our cloud.

Key job responsibilities:
Your responsibilities will include, but not be limited to:
Utilizing testers and system boards in combination with optical debug and fault isolation (FI) techniques such as: laser stimulation operations (OBIRCH, LADA, etc.), laser probing and emission microscopy.
Root cause failures and performance limitations and drive decision making related to test coverage and yield issues.
Analyzing and diving deep into fundamental aspects of material/device operations and light-matter interactions.
Owning the development of electrical, analytical and mechanical methodologies to ensure strategic failure analysis capabilities for future technologies and products.
Using test diagnostic techniques.
Working directly with other teams: Test, DFT, HW, SW, Backend, Q&R & foundry.
Research and development of novel and new debug techniques.

We are looking for exceptional software engineers to help develop the next generation chips based on a revolutionary architecture.
In this job you will design and develop software for functional and performance validation.

Key job responsibilities:
In this role you will develop system level software, targeting chip architecture, functional correctness and performance, running on various platforms and validating chip functionality.

We are looking for a Senior Application Engineer to join a global team of Application Engineers that own a technical success and customer satisfaction across multiple high-impact projects.
Requirements
Responsibilities
Provide close support to customers and deploy our technology across multiple projects
Provide training to customers on our tools and present our technology
Ability to plan, prioritize tasks/issues and take them to full resolution
Provide continuous feedback to R&D to improve the product.

The Signal-Integrity & Packaging (SIP) team manages the external electrical interfaces of Annapurna Lab's chip devices, focusing on signal integrity, power integrity, and electrical usage.
The team collaborates with the BackEnd team to integrate interfaces into the die, designs package layouts for BGA substrates, and conducts signal and power integrity simulations. The team partners with the system team to develop optimal pin-out and PCB breakout schemes, performs electrical characterization of interfaces, and develops software tools for debug and diagnostics.

As a SIP team member, the scope of your work will be focused on Package substrate layout, with a blend of Signal & Power integrity extractions and simulations, as well as also influencing the DIE I/O structures.

Key job responsibilities:
Design and Layout of large and complex package substrates.
Understanding package substrate technologies and layout design rules.
Proficiency in Signal and Power Integrity considerations.
Layout test studies of Die bump-out structures and Package substrate breakout.
Layout test studies of Package pin-out arrangements and PCB board implementation.
Continuously improve the package design work, by coming up with initiatives that drive efficiency, and in turn help improve quality/cost/schedule of the package layout work.

The position is for an entry level, and we will teach and mentor all aspects of the role. No prior hands-on experience in the above list is required.

We are looking for a Senior Machine Learning Algorithm Engineer who is passionate about solving complex, real-world problems at the intersection of hardware and software.
Location: Haifa \ Tel-Aviv in hybrid model.
Responsibilities
Develop advanced ML algorithms using data from our company Agents embedded in silicon. Example domains include:
Lifetime predictions
Clustering and dimensionality reduction
Parametric modeling and screening
Time-series forecasting
Lead end-to-end algorithm lifecycle: ideation → research → POC → design → implementation → validation → deployment.
Collaborate closely with cross-functional teams and directly with customers to continuously refine and enhance deployed solutions.
Drive integration of AI-enhanced tools and intelligent pipelines into ML workflows.

We are looking for a Senior ASIC Physical Design Engineer to join our dynamic team, Join the ride as we spearhead the next revolution in electronics!
What Youll Do
Own and continuously improve our smooth product backend integration methodology, flows, and best practices using Cadence and Synopsys tools.
Develop, maintain, and scale automation and infrastructure (TCL / Python) to improve quality, predictability, and turnaround time.
Collaborate closely with multiple teams to ensure smooth handoffs and high-quality product.
Support field teams on complex technical issues when needed.
Responsibilities
Implementation of ASIC units using advanced flows
Developing BackEnd methodology using Cadence and Synopsys tools
Build and develop scripts for physical design implementation
Support Field team with customer issues.

FPGA Verification engineer We are seeking a talented and experienced FPGA Verification engineer to join our hardware development team. In this role, you will be responsible for defining and executing comprehensive verification strategies for complex FPGA-based systems, from architectural definition through system integration. You will work closely with FPGA designers, system architects, algorithm teams, and board designers to ensure high-quality and robust designs using advanced verification methodologies and tools.
Key Responsibilities
Develop and maintain advanced verification environments using SystemVerilog and UVM
Write testbenches, behavioral models, monitors, and scoreboards
Create directed and constrained-random TEST scenarios
Execute simulations, analyze results, and perform in-depth debugging
Define and track functional and code coverage metrics
Collaborate with design engineers to identify and resolve design issues
Support system integration and bring-up activities
Contribute to verification planning and documentation.

We are looking for a Senior Product Engineer to join a global team of a Product Engineers that own a technical success and customer satisfaction across multiple high-impact projects. This role is deeply rooted in data analytics; youll be working at the intersection of silicon, systems, and software to deliver high-value insights to customers.
Responsibilities
Performing post-silicon and system-level data analysis and providing insights on data extracted from post-silicon stages
Supporting customers with analytics platform problems solving and new features introduction
Drive integration of our companys analytics platform within customer environments, bridging silicon, test, and system-level domains.
Collaborate with R&D and data science teams to develop, validate, and improve advanced analytics algorithms.
Troubleshoot complex silicon/system issues through data-driven insights.
Partner with internal stakeholders (design, software, product) to influence roadmap and execution.
Act as a technical proffesional in customer onboarding, support, and ongoing engagement.

As formal Verification Engineer you'll own verification tasks from planning through execution, collaborating with experienced engineers across multiple teams to ensure design quality while meeting challenging timelines of the Graviton product line. This is an excellent opportunity for motivated engineers to grow their formal verification expertise in a supportive, high-impact environment.

Key job responsibilities:
Plan and execute formal verification plans under guidance from senior engineers.
Develop formal test-benches for design modules.
Debug formal verification failures and analyze root causes.
Collaborate with design and verification teams to resolve issues.
Learn and apply new formal verification methodologies and tools.

we are looking for a Senior VLSI Verification Engineer to join the ride as we spearhead the next revolution in electronics!
Position location: in our Haifa or TLV offices, at least 2 working days at Haifa site (Hybrid model)
Responsibilities
Develop and maintain advanced verification environments using SystemVerilog and UVM, ensuring scalability, configurability, and reusability across multiple IPs.
Design, implement, and execute comprehensive testbenches and random test suites to validate functional correctness, robustness, and corner-case behavior of complex IP within various SoC integration environments.
Drive coverage closure by defining, collecting, and analyzing code and functional coverage metrics; identify verification gaps and ensure complete validation of feature sets prior to sign-off.
Lead debug and root-cause analysis efforts in collaboration with senior verification and design engineers, leveraging carefully crafted logs, waveform analysis and assertions to isolate and resolve design or environment issues.
Collaborate closely with architecture, design, and firmware teams to ensure verification completeness, alignment with design intent, and seamless integration at the system level.
Contribute to methodology and infrastructure improvements, including reusable UVM components, automation scripts, and best practices that enhance team efficiency and verification quality.

We are looking for talented Engineers to join our Virtual Platforms team.
Virtual platforms play a crucial role in accelerating the development process by enabling early Software development, System-Level testing, and architectural exploration without the constraints of physical prototypes.

As a Virtual Platform Engineer, you will:
Develop accurate and efficient simulation models of hardware components.
Create and maintain Virtual Platform environments for software development and system-level validation.
Debug and optimize complex hardware-software interactions.

This role requires strong communication skills and a collaborative mindset, as you'll frequently interact with various teams across AWS to deliver optimal solutions.

If you are passionate about shaping the future of semiconductor technology and meet our qualifications, we invite you to join our dynamic team. Let's redefine what's possible together!

As Chief Engineer, you will be responsible for ensuring that all electrical, mechanical, and fire/life safety equipment within the data center is operating at peak efficiency. This involves planned preventative maintenance of equipment, daily corrective work, and emergency response. You are expected to be a singular focal point for all facility operations and to support Amazon within its owned and operated data centers.

You should be able to manage large scale impacting projects and new region support from conception to completion. These projects involve large amounts of independent work as well as collaboration with external support groups including engineering, automation, procurement, and finance in both local and global settings. As Chief Engineer, you will be tasked with creating and delivering on key milestones, obtaining and tracking quotes for all necessary costs, and documenting project results for future implementation at other facilities. The goals of such projects are for the Chief Engineers to drive innovation and resiliency while reducing operational costs in the facilities.

Key job responsibilities:
Train and support the Engineering team in their role of providing electrical and mechanical equipment troubleshooting and operations.
Implement and execute site or equipment-specific training exercises. Exercises cover, but are not limited to: stand-by diesel generators, switchgear, UPSs, PDUs, AHUs, chillers etc.
Oversee day-to-day operation and maintenance of mechanical and electrical equipment in data center sites.
Operate independently, with limited direct management.
Assist in the design and build-out of new facilities and perform root cause analysis of equipment failures.
Act as an escalation point for all facilities-related issues within the data center region. Work OT hours as needed to support site stability.
Troubleshoot and report facility and data sever-level events within internal Service Level Agreements (SLA).
Create and deploy standard practices for Engineering Operations Technicians, Chief Engineers, and vendor support teams.
Ensure all safety procedures are adhered to by vendors, and AWS staff.

As a System Lead Engineer in the Nitro team, you will be responsible for defining Annapurna Labs Network Interface Card (NIC) hardware. Following the development and validation of our NIC, and bringing the NIC to mass production.

Youll provide leadership in new technologies of the HW interfaces, bringing them to large-scale deployment, in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and youll work with technical experts, senior leaders, and multiple areas of technology.

Key job responsibilities
As Lead engineer youll get involved with the first architecture discussions and through design development, readiness to production until product exposure to customer. Youll handle hardware and software system related aspects, such as: architecture definition, mechanical design, thermal and power design, signal integrity of high speed interfaces (PCIe, High Speed Ethernet and DDR), boot flows, recovery flows, remote debug hooks, firmware live-update flows, system health monitoring sensor, report flow, etc... This is a fast-paced, intellectually challenging position, and youll work with thought leaders in multiple technology areas. Youll have high standards for yourself and everyone you work with, and youll be constantly looking for ways to improve your products performance, quality and cost. Were changing an industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today.