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we are now looking for a chip design Verification engineer to join the chip design methodologies team. the team is in charge of the verification methodologies, shared code, training, and embracing new technologies. one of our main goals is to make sure that the team works in an efficient manner, and provides high-quality deliveries. this position offers the opportunity to have real impact in a dynamic, technology-focused company.
what you'll be doing:
develop shared verification code and solutions to be widely used by the chip design team.
develop groundbreaking methodologies to create a flawless experience for Verification engineers to keep the focus on new problems.
collaborate with the design automation team to provide end-to-end solutions that combine verification, simulation, and automation.
get in touch with eda vendors to learn about cutting-edge tools/technology and apply them into our verification process.
understand the design, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
collaborate with designers, verification specialists to accomplish your tasks.
develop training sessions.

looking for firmware engineer to join a team that works on nvidia ethernet switch. you will take part as a fw micro architect in full-cycle firmware development for new and existing products using modern software development tools and approaches.
if you're creative, responsible, hardworking, and autonomous, we want to hear from you!
what you'll be doing:
closely work with sw & hw architecture and different software develop teams to define the fw architecture for new features/improvements.
identify & diagnose high-value data path performance issues.
aim for high quality thinking and creative ways to improve fw performance, scalability and working methodologies.
you will learn how a big software project is operated, maintained, qualified and released, and how hardware and firmware are developed.
collaborate with other nvidia r&d teams around the globe.

seeking a visionary ai Verification engineer to join our chip design methodologies team. were expanding how we use ai across all our verification methods. in this role, youll help us figure out where ai fits best and build the 'brains' behind our tools. youll help us leverage ai, utilizing llms and Machine Learning -to help us debug complex chips faster and more efficiently
what youll be doing
ai ecosystem development: build and deploy an ai verification environment, moving from manual testbenches to automated stimulus generation and coverage closure.
next-gen tooling: develop and integrate ai agents and ml models directly within the verification toolchain to automate intent-to-testbench workflows.
intelligent debugging: create and refine ai-based debug assistants that can analyze simulation failures, categorize bugs, and suggest fixes autonomously.
methodology innovation: research and apply groundbreaking ai approaches (such as reinforcement learning or llms) to address the "state-space explosion" in chip verification.
collaborative intelligence: work with design automation teams and eda vendors to ensure our ai solutions provide end-to-end efficiency from rtl to gds.
leadership & training: act as the authority, training the broader team on how to bring to bear ai tools and "human-in-the-loop" methodologies.
nvidia houses the most forward-thinking minds in the world. are you a creative engineer ready to build the first truly self-verifying chip environment? come join our team and help us define the future of hardware powered by artificial intelligence.

we are now looking for a versatile, fast learner, and highly motivated fe integration and eda tools engineer! as a member of our switch organization, you will be part of frontend integration and eda flows for a highperformance, lowpower switch chip. our fei team drives methodologies, automation, and quality for our frontend implementation and cd/ci, working closely with architecture, design, verification, and backend teams. this position offers you the opportunity to have real impact in a dynamic, technologyfocused company influencing future switch product lines. 
what you'll be doing:
driving frontend integration of major blocks in a pioneering ethernet switch asic, from rtl handoff through synthesis and signoff checks.
building, maintaining, and improving eda flows and methodologies for the switch org (lint, cdc/rdc, formal, synthesis/uls, fedct/fefc and related frontend signoff flows).
working closely with logic design and microarchitecture teams to define integration constraints, clocks/resets, interfaces, and quality targets.
partnering with dv, be, and cad/flow teams to ensure robust, scalable, and efficient frontend implementation across the project.
developing automation and infrastructure (scripts, regression flows, dashboards) to improve productivity, and debuggability.
debugging complex tool, flow, and design issues; driving rootcause analysis and longterm methodology improvements.

we are looking for a formal Verification engineer for our nvidia networking team!
this is an exciting opportunity to join a hardworking pre-silicon design and verification team, working on groundbreaking switch and gpu technologies. we deploy state-of-the art formal verification tools and methodologies to prove design correctness. working in our formal verification team will expose you to a wide range of cutting edge design and technologies that are in the heart of th ai revolution. our team delivers world class chips solutions for hpc, ai infrastructures, data -center, network, and Storage markets. we micro-architect, verify, and deliver smart and high bandwidth multi port switches. nvidia has the most sophisticated formal tools and methodologies in the industry, which help us achieve a0 design tapeouts. as part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
what you'll be doing:
in this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
you will work on ambitious designs along with our pre-silicon team and take part in developing the next generation of nvidia's core technology.
you will take part in the ai revolution led by nvidia, working on cutting edge architecture.

We are looking for an experienced System Engineer to lead the definition and integration of our next-generation wireless IoT systems. You will possess a unique "end-to-end" perspective: understanding the physics of the RF/Analog silicon, the intricacies of the BLE protocol, and the full integration between devices to network connectivity. You will work closely with Silicon, FW, and Cloud teams to ensure robust connectivity and optimized power consumption.

Responsibilities:
System Architecture: Define system-level requirements for Wireless IoT products, focusing on RF performance, power budgets, and data throughput. Faimilairy with in-door wireless including antenna design consideration is an advantage.
Silicon & RF Interface: Work with Silicon development teams to define RFIC specs and resolve integration challenges (Analog/RF mixed-signal flows).
Connectivity Pipeline: Define the HW to Firmware to Ethernet or wireless pipeline.
Integration & Debug: Hands-on bring-up of new silicon/hardware in the lab, debugging complex issues spanning from RF interference to network protocol failures.

We are looking for a System Engineer who "speaks" both Network and Code. In this role, you will be the architect of the systems connectivity, designing how our devices communicate over wired LAN infrastructures and ensuring the software architecture supports robust, high-throughput data flow. You will bridge the gap between IT network configuration and R&D software development.

Responsibilities:
System Network Design: Define the networking architecture for complex systems, focusing on Wired LAN configurations, switch management, and topology planning.
E2E device to platform SW features: Collaborate with SW teams to define system-level software features - for example security, configurations, etc...
Network Integration: Lead the integration of system components into customer IT environments (Subnets, VLANs, Firewalls).
Hands-on Coding: Write production-grade code or advanced scripts for system automation, network simulation, and performance testing.
Bottleneck Analysis: Analyze data flows to identify network congestion or software inefficiencies and propose architectural changes.
Security: Define and implement network security protocols (PKI, penetration resilience) within the system design.

we are now looking for a senior chip design rtl design engineer for the switch silicon group.
as a chip design engineer at nvidia's networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
work in a combined design and verification team which develops some of the switch silicon core units.
plan and design rtl units / blocks according to arch & micro arch specifications under challenging constraints with high orientation to power, area, and performance.
build reference models, verify and simulate chip blocks/entities according to specifications.
work closely with multiple teams within organizations such as architecture, micro- architecture, and fw.

looking for outstanding chip design Verification engineers to join our networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
what you will be doing:
work in a combined design and verification team which develops core units within the networking silicon.
build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
work closely with multiple teams within organizations such as architecture, micro- architecture, full-chip, fw and post-silicon validation.
your daily work will involve all aspects of design verification: planning, coding, coverage and integration

we are now looking for an arch simulation manager to join our nvidia networking team! as a switch-arch simulation manager in nvidias networking business unit, you will lead a team of highly skilled hardware engineers responsible for verifying the next generation of nvidias cutting-edge switch products. this is a unique opportunity to make a real impact at the heart of nvidias ai and hpc revolution, while working in a fast-paced, innovative environment. you will be part of a passionate and experienced team using modern approaches to validate the performance requirements for the next generation of nvidia networking products. your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and Storage applications.
what youll be doing:
lead and grow a team of hardware Verification engineers focused on arch performance validation of complex digital designs.
collaborate closely with architecture, design, dv teams to identify verification needs and drive closure.
provide technical guidance, mentoring, and support to engineers in the team.
own the planning and execution of simulation deliverables to ensure high quality and timely tapeouts.

we are now looking for a senior verification manager for our fc switch silicon team. as a fullchip verification manager in networking business unit, you'll lead a group of passionate engineers to design and implement the next generation state-of-the-art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
work in a fc team, responsible to integrate and verify the switch at system level
lead and grow a team of fullchip Verification engineers
responsible to drive the fullchip verification execution, including staging plan of the projects and deliveries
provide technical guidance, mentoring, and support to engineers in the team.
work closely with multiple teams within organizations such as architecture, u-arch, full chip micro-architecture, be, and fw
dynamic verification environments planning for units infrastructures and system level
work with design/verification team which develops core units within the switch silicon.

we are looking for a senior firmware Verification engineer to define, develop and maintain verification for our ethernet switches. this role offers you an excellent opportunity to participate in the development process of switches and gain a deep understanding in hardware, firmware and software systems in a rapidly growing field.
what youll be doing:
closely work with sdk/fw r&d architecture and QA to define, write and implement TEST plan for out product existing new features.
be responsible for verification and delivering different networking features.
define, develop and maintain verification procedure and reference model infrastructure - make TEST suites robust.
work with continuous integration system, regression tools, automate builds, run TEST suites and analyzing results
we are an equal opportunity employer and value diversity at our company. we do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

we are looking for a dedicated SOC clocks design automation engineer to join our networking silicon team. in this role, youll focus on developing and supporting clock-related design flows and methodologies for SOC and networking chips, ensuring efficient and high-quality design implementation. youll also chip in to SOC top-level automation and integration activities, building on existing flow infrastructure to improve efficiency and consistency across projects. introduction
what you'll be doing:
develop and maintain design automation and methodologies for SOC and networking clock flows.
collaborate with design, sta, and project teams to ensure timely and high-quality design closure.
develop and improve SOC top-level automation scripts and flows built upon existing infrastructure and tools.
support SOC integration and construction flow activities across multiple projects.
assist in timing, power, and noise analysis to ensure efficient performance.

we are now looking for a formal verification manager to join our networking team!
as a formal verification manager in networking business unit, you will lead a team of highly skilled formal engineers responsible for verifying the next generation of cutting-edge network products and gpu technologies.
this is a unique opportunity to make a real impact at the heart of ai and hpc revolution, while working in a fast-paced, innovative environment.
you will be part of a passionate and experienced team using leading formal verification tools and methodologies to ensure design correctness at the highest level. your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and Storage applications.
what youll be doing:
lead and grow a team of formal Verification engineers focused on pre-silicon formal verification of complex digital designs.
define and drive formal verification strategies and methodologies to prove the correctness of designs across multiple projects.
collaborate closely with architecture, design, dv teams to identify verification needs and drive closure.
provide technical guidance, mentoring, and support to engineers in the team.
own the planning and execution of formal verification deliverables to ensure high quality and timely tapeouts.

ethernet switch firmware team is looking for a hardworking firmware manager to take part in leading and developing the firmware / hw interface in the next generation state of the art switch products.
as a member of our fw ethernet team, you will be responsible on a team of firmware engineers. it is expected that you will manage and guide the team for critical items.
this role offers you an excellent opportunity to accomplish something new, enabling understanding of hw and sw in a rapidly growing field while solving interesting technical issues and providing feedback to the hw team to improve the next asic generation.
what you will be doing:
lead a team of engineers and provide technical guidance to the team of highly skilled engineers. empower the team members to excel and increase team productivity.
lead the design and implementation of new features in the core of switch networking firmware.
drive and facilitate the planning, scheduling, and execution of the project and activities of the team
collaborate with architecture and different software design teams as part of the software development lifecycle.
work in pre and post-silicon development environments of next-generation switch networking products.
gain a deep understanding of networking technology, system debugging, and stacks, as well as the hw/fw/sw relationship.
innovate! bring networking products to shine in customers view