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5 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
we are now looking for a chip design Verification engineer to join the chip design methodologies team. the team is in charge of the verification methodologies, shared code, training, and embracing new technologies. one of our main goals is to make sure that the team works in an efficient manner, and provides high-quality deliveries. this position offers the opportunity to have real impact in a dynamic, technology-focused company.
what you'll be doing:
develop shared verification code and solutions to be widely used by the chip design team.
develop groundbreaking methodologies to create a flawless experience for Verification engineers to keep the focus on new problems.
collaborate with the design automation team to provide end-to-end solutions that combine verification, simulation, and automation.
get in touch with eda vendors to learn about cutting-edge tools/technology and apply them into our verification process.
understand the design, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
collaborate with designers, verification specialists to accomplish your tasks.
develop training sessions.
Requirements:
what we need to see:
a bachelors degree in electrical engineering or Computer Science.
exposure to design and verification tools.
5+ years of hands-on pre-silicon verification experience.
strong interpersonal skills and ability & desire to innovate.
ways to stand out from the crowd:
experience in Specman / system verilog uvm.
understanding simulation tools.
experience in building TEST benches, evaluate coverage and debug simulation failures.
This position is open to all candidates.
 
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22/03/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are seeking a Principal verification engineer to be a technical lead in the chip design methodologies team. The team is in charge of the verification methodologies, shared code, training, and adopting new technologies. One of our main goals is to define, build and use best in class technologies make sure that the chip design team works in an efficient manner and provides high-quality deliveries at scale. This position offers the opportunity to drive foundational flows and have a profound impact in a dynamic, technology-focused company.

What you'll be doing:

Define groundbreaking methodologies to create a flawless experience for verification engineers.

Mentor and guide designers and verification specialists to tackle complex technical challenges.

Identify design risks, define the verification scope, and lead infrastructure development to ensure design correctness.

Technically guide the development process of shared verification code and infrastructure to be widely used by the global chip design team.

Partner with the design automation team to provide end-to-end solutions that unify verification, simulation, and automation.

Collaborate with EDA vendors to learn about innovative tools/technology and integrate them into our long-term verification strategy.

Lead verification strategies, training sessions.
Requirements:
What we need to see:

A Bachelors Degree in Electrical Engineering or Computer Science, or equivalent experience.

Comprehensive mastery of design and verification tools.

15+ years of hands-on pre-silicon verification experience with a track record of technical leadership.

Exceptional interpersonal skills and ability & proven track record to promote innovation.

Ways to stand out from the crowd:

Experience leading processes across multiple groups and driving meaningful, influential change in the verification lifecycle.

Deep knowledge of simulation tools and performance optimization.
This position is open to all candidates.
 
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5 ימים
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
we have been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. its a unique legacy of innovation thats fueled by great technology-and amazing people. today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world.
the complexity of the chip has greatly increased over the years. we are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. thesystem -on-chip ( SOC ) group is seeking a top SOC Verification engineer to verify the design and implementation of the worlds leading networking socs. in this position, you will get the opportunity to craft complex networking chips and interact directly with architects, designers, and software engineers across sites. this is your chance to shape the future of computing with a world-class team! as an SOC Verification engineer, you will verify the design and implementation of our SOC technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches and nic SOC product lines. we are working closely with a wide range of aspects - chip design, dft, backend, verification and production testing. we are working on the most advanced technologies and complex products. our SOC solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for verification of the clock design elements, architecture and micro-architecture using sophisticated verification methodologies.
as a member of our SOC verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (testbenches, bfms, checkers, monitors), execute TEST /coverage plans, and verify the correctness of the design.
collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.
Requirements:
bsc. in electrical engineering or computer engineering.
2+ years of relevant experience.
good understanding of rtl design (verilog)
experience of uvm methodology.
strong debugging, problem solving and analytical skills.
excellent communication and social skills.
ability to work in a geographically diverse team environment.
self motivated, independent and target oriented.
way to stand out from the crowd:
previous experience in SOC and/or verification
experience in developing verification environments and random based verification for unit level and system level using verification tools (simulation tools, verilog, debug tools like simvision/debussy)
background with sv/uvm and Python
This position is open to all candidates.
 
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5 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
we are looking for a senior chip design Verification engineer for developing the next generation dft technologies.
as a senior chip design Verification engineer in the dft team , you will verify the design and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and complex products. our dft solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for verification of the dft design, architecture and micro-architecture using sophisticated verification methodologies.
as a member of our dft verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (testbenches, bfms, checkers, monitors), execute TEST /coverage plans, and verify the correctness of the design.
collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.
Requirements:
what we need to see:
bsc. in electrical engineering or computer engineering, or equivalent experience.
5+ years of practical verification experience.
experience in developing verification environments and random based verification for unit level and system level using verification tools (simulation tools, verilog, debug tools like simvision/debussy).
experience with Specman is a plus.
good understanding of rtl design (verilog).
strong debugging, problem solving and analytical skills.
excellent communication and social skills.
ability to work in a geographically diverse team environment.
self motivated, independent and target oriented.
This position is open to all candidates.
 
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5 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
seeking a visionary ai Verification engineer to join our chip design methodologies team. were expanding how we use ai across all our verification methods. in this role, youll help us figure out where ai fits best and build the 'brains' behind our tools. youll help us leverage ai, utilizing llms and Machine Learning -to help us debug complex chips faster and more efficiently
what youll be doing
ai ecosystem development: build and deploy an ai verification environment, moving from manual testbenches to automated stimulus generation and coverage closure.
next-gen tooling: develop and integrate ai agents and ml models directly within the verification toolchain to automate intent-to-testbench workflows.
intelligent debugging: create and refine ai-based debug assistants that can analyze simulation failures, categorize bugs, and suggest fixes autonomously.
methodology innovation: research and apply groundbreaking ai approaches (such as reinforcement learning or llms) to address the "state-space explosion" in chip verification.
collaborative intelligence: work with design automation teams and eda vendors to ensure our ai solutions provide end-to-end efficiency from rtl to gds.
leadership & training: act as the authority, training the broader team on how to bring to bear ai tools and "human-in-the-loop" methodologies.
nvidia houses the most forward-thinking minds in the world. are you a creative engineer ready to build the first truly self-verifying chip environment? come join our team and help us define the future of hardware powered by artificial intelligence.
Requirements:
what we need to see
bachelors degree in electrical engineering, Computer Science, or equivalent experience.
7+ years of hands-on pre-silicon verification experience.
strategic innovation: a perspective geared toward automation and a desire to redefine traditional "manual" verification workflows.
ways to stand out from the crowd
ai for eda: experience building or using ai tools specifically designed for hardware verification (e.g., automated coverage, log analysis, or bug prediction).
This position is open to all candidates.
 
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5 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
looking for outstanding chip design Verification engineers to join our networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
what you will be doing:
work in a combined design and verification team which develops core units within the networking silicon.
build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
work closely with multiple teams within organizations such as architecture, micro- architecture, full-chip, fw and post-silicon validation.
your daily work will involve all aspects of design verification: planning, coding, coverage and integration
Requirements:
what we need to see:
b.sc or above in electrical engineering or computer engineering, graduation with high scores.
5+ years of validated experience in chip design dynamic verification.
professional verification experience, knowledge in advanced verification methodologies and tools.
demonstrates deep understanding in design and verification logic.
strong debugging, problem-solving and analytical skills.
a great teammate with strong communication and interpersonal skills.
self-motivated, ability to work independently and drive tasks to completion.
ways to stand out from the crowd:
experience in developing verification environments in Specman.
prior design or verification experience of high-speed interconnects and/or SOC.
knowledge in network flows and protocols.
This position is open to all candidates.
 
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5 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? our engineering team works on groundbreaking innovations involving crafting creative solutions for dft architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. we are looking for an experienced dft engineer to join the atpg team. the position includes taking part in development of the next generation dft technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
 
working on the most advanced technologies and complex products, our dft solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
 
what youll be doing:
you will be in charge of state of the art design for TEST /atpg flows and implementation
take full atpg ownership end to end on a project, from arch & planning to pattern generation, verification and post silicon bring up and diagnosis.
inventing and maintaining automation flows that provide the short TEST time to production
Requirements:
5+ years of hands on dft/atpg experience knowledge & technical experience in dft asic design and in atpg tools
strong programming skills in scripting languages
bsc. in electrical engineering or computer engineering
quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility
 
ways to stand out from the crowd:
knowledge of dft including scan, bist, on-chip scan compression, fault models, atpg, and fault simulation
experience in mentor testkompress atpg tool and retargeting flow
programming languages: tcl, prl, phyton & Unix shell scripts
experience with ate and silicon bring-up
 
This position is open to all candidates.
 
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5 ימים
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
we are now looking for a formal verification manager to join our networking team!
as a formal verification manager in networking business unit, you will lead a team of highly skilled formal engineers responsible for verifying the next generation of cutting-edge network products and gpu technologies.
this is a unique opportunity to make a real impact at the heart of ai and hpc revolution, while working in a fast-paced, innovative environment.
you will be part of a passionate and experienced team using leading formal verification tools and methodologies to ensure design correctness at the highest level. your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and Storage applications.
what youll be doing:
lead and grow a team of formal Verification engineers focused on pre-silicon formal verification of complex digital designs.
define and drive formal verification strategies and methodologies to prove the correctness of designs across multiple projects.
collaborate closely with architecture, design, dv teams to identify verification needs and drive closure.
provide technical guidance, mentoring, and support to engineers in the team.
own the planning and execution of formal verification deliverables to ensure high quality and timely tapeouts.
Requirements:
bsc or msc in electrical/computer engineering, Computer Science, or mathematics.
5+ years of managerial experience in a chip design or verification domain.
8+ years of overall industry experience in formal verification, functional verification, or rtl design.
deep understanding of formal verification concepts, tools, and flows.
excellent leadership, problem-solving, and communication skills.
strong analytical and debugging abilities.
ways to stand out from the crowd:
hands-on experience with formal verification
background in developing formal testbenches, assertions, and coverage models.
managerial experience in chip design domain
a passion for recruiting, leading, mentoring engineers and building strong, collaborative teams.
This position is open to all candidates.
 
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22/03/2026
Location: More than one
Job Type: Full Time
Our Formal Verification (FV) team is seeking a visionary AI Verification Engineer to join our elite Networking Chip Design group. Our team is unique: we define the infrastructure and drive the methodologies for proving the correctness of the worlds most advanced AI and networking architectures. We operate at the cutting edge, leveraging a sophisticated ecosystem of proprietary in-house formal tools and industry-leading vendor EDA solutions.

In this role, you will be a key architect in our "AI-for-FV" evolution. You will work in close collaboration with our internal CAD and Design Technology AI teams to enhance our in-house toolset with artificial intelligence. You won't just be using tools; you will be building the "brains" that sit on top of them-utilizing LLMs and Machine Learning to automate intent-to-proof workflows and debug complex chips with unprecedented speed.

What Youll Be Doing:

In-House Tool Evolution: Partner closely with internal CAD teams to integrate AI capabilities directly into our proprietary FV infrastructure.

Methodology Architecture: Define and evolve the FV teams specialized methodologies, moving from manual property writing to AI-automated assertions.

Next-Gen Orchestration: Develop and integrate AI agents and ML models that interface with our toolchain to automate "intent-to-assertion" workflows and optimize coverage and convergence.

Intelligent Debugging: Create AI-based debug assistants that analyze formal counter-examples, categorize failures, and autonomously suggest fixes for complex logic problems.

Collaborative Intelligence: Act as the bridge between the FV team, Design Technology AI, and CAD groups to ensure our AI solutions provide end-to-end efficiency from RTL to A0 tapeout.

Leadership & Training: Act as the authority on AI integration, training the broader team on how to leverage "human-in-the-loop" AI tools and automated methodologies.
Requirements:
What We Need to See:

Bachelors or Masters Degree in Electrical Engineering, Computer Science, or equivalent experience.

7+ years of hands-on pre-silicon verification experience, with a strong foundation in Formal Verification (FV).

A perspective geared toward automation and experience, defining or refining complex verification infrastructures.

A desire to redefine traditional "manual" verification workflows using modern software and AI principles.

Ways to Stand Out from the Crowd:

Experience building or deploying AI tools specifically designed for hardware (e.g., LLM-based assertion generation)

Proven track record of collaborating with CAD or tool-development teams to refine internal design flows.
This position is open to all candidates.
 
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5 ימים
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? our design-for- TEST engineering team works on groundbreaking innovations involving crafting creative solutions for dft architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. we are looking for a dft engineer to join the atpg team. the position includes taking part in development of the next generation dft technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
working on the most advanced technologies and complex products, our dft solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
Requirements:
you will be in charge of state of the art design for TEST /atpg flows and implementation
take atpg ownership on different dft aspects of a project, arch & planning, pattern generation, verification and post silicon bring up and diagnosis.
inventing and maintaining automation flows that provide the short TEST time to production
what we need to see:
b.sc. in electrical engineering or computer engineering or equivalent experience
5+ years of hands on dft/atpg knowledge & technical experience in dft asic design and in atpg tools
strong programming skills in scripting languages
quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility
ways to stand out from the crowd:
knowledge of dft including scan, mbist, lbist, on-chip scan compression, fault models, atpg, and fault simulation
experience in mentor testkompress atpg tool and retargeting flow
programming languages: tcl, prl, phyton & Unix shell scripts
experience with ate and silicon bring-up
This position is open to all candidates.
 
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5 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
seeking a dynamic and highly motivated senior Software manager to lead our software verification and automation for doca networking sdk. we are looking for a candidate who can excel in a sophisticated, multidisciplinary environment, take ownership, and drive high-quality verification and automation processes. this position offers the opportunity to have a real impact on sophisticated, groundbreaking products, delivered by nvidia and developed by our customers, empowering the most advanced data centers in the world. this role requires close collaboration with teams across various fields (sw, hw, QA ) to elevate our product to the next level.
what you'll be doing:
lead teams of software Verification engineers, providing technical direction, career development, and performance mentorship
define and continuously refine our software testing methodology and processes
engage in a hands-on approach, actively participating in the design, coding, and debugging of verification tests and infrastructure alongside your team
lead the verification process, ensuring the functionality, stability, and performance of our doca networking sdk and the solutions on top of it
work closely with internal and external customers to understand system use cases
analyze coverage measures to identify verification gaps and provide data -driven insights into product development and release readiness
Requirements:
what we need to see:
b.sc degree or equivalent experience in Computer Science, computer engineering, or electrical engineering
10+ years of overall professional experience and 4+ years of experience managing managers or senior engineers.
proficient in Python, C, C ++ with the technical depth to guide and mentor the team
experience with regression systems and their optimizations
experience with networking protocols, mainly ethernet
experience with virtualization technologies
strong analytical, debugging, and problem-solving skills with meticulous attention to detail
experience with Embedded sw development
excellent interpersonal skills and the ability to multitask in a dynamic environment with shifting priorities
self-motivated and well-organized
ways to stand out from the crowd:
advanced understanding in ethernet protocols and rdma
experience with cloud and ai workload optimization
proficiency in continuous integration (ci) methodologies and tools such as gerrit, jenkins, and gitlab
experienced in TEST generation and coverage methods and metrics
background in Linux Kernel, security protocols
This position is open to all candidates.
 
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