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As we expand our presence in Israel, we're seeking a visionary System Validation Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.


Job Description
The mission of this role is to perform system validation for our highly advanced devices, that includes defining strategy, develop tools, innovate, be creative to make sure devices are performing as they should in all aspects, logical, performance, durability, stress and more.

You will be part of the site located at Israel (Haifa - Matam), surrounded with highly experienced and professional engineers who will escort, mentor and support you on your journey in our company.

We are looking for a Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams.

Key Responsibilities
Perform hands-on post-silicon validation.
Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability.
Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.
Drive complex issues from initial failure through root-cause analysis and final resolution.
Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.
Validate PCIe functionality across different generations, platforms, configurations, and operating conditions.
Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.
Develop automation to improve validation coverage, debug efficiency, and regression testing.

As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.


Key Responsibilities
Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments.
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence.
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments.
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners.
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient.

As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip.
Collaborate closely with Physical Design team to insure a full power integrity
Be responsible on IR architecture for timing convergence.
Partner with Package Design engineers to perform Chip-Package co-analysis (CPM).
Understand root-cause analysis for voltage drop violations and EM risks.
Be responsible and go-to person for any IR related issues.

As we expand our presence in Israel, we're seeking a talented Staff/ Principal Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.

As a Staff/ Principal Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified

Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices

Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment

As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the worlds largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities
Execute SoC Top-level physical design and actively drive full-chip convergence.
Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff.
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR).
Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon.
Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration.

As we expand our presence in Israel, we're seeking a talented Staff / Principal ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.

As a Staff / Principal ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support.
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions.
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams.

Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient.
Apply design techniques to meet PPA (Power, Performance, Area) targets.
Contribute to design quality through verification and validation activities.

Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives.
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter.
Collaborate effectively across teams to ensure seamless integration.

As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip.
Collaborate closely with Physical Design team to insure a full power integrity.
Partner with Package Design engineers to perform Chip-Package co-analysis (CPM).
Understand root-cause analysis for voltage drop violations and EM risks.

As we expand our presence in Israel, we're seeking a visionary Staff DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.

As a Staff DFT Engineer, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.

Key Responsibilities

DFT Architecture & Strategy
Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support.
Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards.
​DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies.

Test Pattern Development & Optimization
Generate and optimize high-quality test and debug patterns for production.
Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance.
Drive test coverage and quality metrics to meet stringent manufacturing requirements.

Cross-Functional Collaboration & Methodology Innovation
Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR.
Participate in developing and maintaining cutting-edge DFT implementation flows.
Automate and improve methodologies using advanced scripting and tools.

As we expand our presence in Israel, we're seeking a visionary Silicon Technical Program Manager to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Technical Program Manager, you will be the key architect of our silicons operational reality. You wont just track timelines - you will help establish our local execution culture and technical standards, owning the cross-functional journey of transforming complex logic into high-performance silicon.

Key Responsibilities
Drive and manage ASIC development and subsystems from concept through to production in collaboration with internal teams and external vendors.
Provide hands-on program management throughout the full development cycle of silicon and firmware, including concept, design, development, fabrication, validation, and production release.
Work closely with the software, hardware, and architecture teams to align with product requirements and ensure all constraints are met.
Lead process improvements across multiple teams and functions to drive better collaboration and efficiency.
Independently manage complex projects with minimal supervision, ensuring timelines and milestones are met.
Deliver high-quality ASIC solutions products while collaborating with product management and architecture teams.

We are seeking a motivated Senior System Validation Engineer to join our growing post-silicon validation team in Israel and support next-generation connectivity products for AI and data-center applications.
In this role, you will perform system-level post-silicon validation, characterization, and debug across silicon, hardware, firmware, and software. You will support silicon bring-up and PVT/corner testing, develop and execute functional and system validation tests, analyze results, and work with cross-functional teams to identify and resolve complex system issues.
This is a highly hands-on lab position. The primary location is Haifa, with temporary support at the Ramat Gan lab as needed.
Key Responsibilities:
Develop and execute post-silicon functional and system validation from silicon bring-up through production readiness.
Run PVT, silicon corner, stress, characterization, and qualification testing across a wide range of operating conditions.
Develop validation tests to verify functionality, performance, stability, power, and operating margins.
Debug issues across silicon, hardware, firmware, drivers, and system software.
Validate high-speed interfaces such as PCIe, CXL, Ethernet/SerDes, and DDR, as well as common system interfaces.
Develop Python scripts and automation to improve validation coverage, regression, and test efficiency.
Analyze validation data, identify issues and trends, and drive problems to root cause and closure.
Work closely with hardware, architecture, firmware, software, design, and DV teams to investigate and resolve issues.
Support the transition of new silicon from initial bring-up to a qualified, production-ready product.
Operate system platforms and laboratory equipment to support validation and debug.
Document test results, issues, root cause, and recommendations and communicate findings clearly.

As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution
Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing

Signoff & Design Integrity
Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness

Methodology Development & Cross-Functional Collaboration
Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust

As we expand our presence in Israel, we're seeking a highly skilled Front-End CAD Engineer to join our local engineering powerhouse from the ground up.

As a Front-End CAD Engineer, you will be the backbone of our chip design ecosystem. You wont just be using tools; youll be architecting the methodologies, automation scripts, and design flows that enable our hardware teams to push the limits of silicon performance. Your work directly impacts the productivity of the design team and the time-to-market for our next-generation processors.


Key Responsibilities
Develop, maintain, and optimize RTL generation tools, building automated IPs and SoC schemes.
Create robust applications using Python and Tcl to automate models build, regression and analysis tools and other assisting tools for all disciplines in front-end flows.
Evaluate and integrate Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, and Mentor Graphics.
Define the methodologies of usage and integrate AI tools in this fast-growing field impacting all VLSI development flows.

As we expand our presence in Israel, we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters.

As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You wont just execute tasks; you will define the Formal verification strategy for chips that drive the worlds largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications.

Key Responsibilities
Own and develop formal verification environments from scratch through to sign-off.
Apply formal verification methodologies and strategies to prove the correctness of intricate designs.
Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements.
Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs.
Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently.
Architect and develop generic, common formal functions and properties to be reused across multiple projects.

As we expand our presence in Israel, we're seeking a talented Senior Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.

As an Senior Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.

Key Responsibilities

Emulation Flow Execution & Implementation
Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging.
Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies.
Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market.

System-Level Debug & Validation
Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs.
Ensure rapid cycles from RTL to functional stability through systematic debug approaches.
Own technical blocks and drive them to completion independently.

Cross-Functional Collaboration
Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios.
Ensure seamless hardware-software integration for AI infrastructure connectivity.
Collaborate with Design and Verification teams to optimize emulation strategies.