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ELECTRICAL ENGINEERING STUDENT (RF AND COMMUNICATION SYSTEMS)
Operating complex technological systems in operational activities
Managing the technological operation in operational activities
Operating and maintaining technological systems in the SIGINT field
Testing, installing, training, implementing, and maintaining the aforementioned systems
Accompanying cellular projects and managing the operational aspect of the project
Planning and conducting experiments with technological systems in the SIGINT field.

At Infinidat, a Lenovo company, we empower enterprises and service providers with cutting-edge storage platforms that redefine performance, reliability, and cyber resilience at scale. If you have a strong background in NPI processes, experience in PLM, strong self-learning capabilities, and leading tasks E2E, we’d like to meet you! The NPI engineer will be responsible for the configuration control of INFINIDAT products, and all aspects of NPI processes.

Responsibilities:

* Building and managing Production files: BOMs, Product documentation, working instructions, and drawings.
* Transfer to Production of new products - Full NPI processes.
* Conducting and implementing product changes (ECOs, deviations) and configuration control, managing product lifecycle E2E.
* Ongoing technical support at FTK sub-contractor's production line sites (IL and US) with existing and new products, an initiative for production line continuous improvement.
* Lead the company certifications and compliance maintenance -International and sustainability.
* Work closely with various departments in the company to define manufacturing procedures.

We are global, with HQ in NYC and R&D centers in Tel Aviv, New York, Finland, Berlin, Belgium and San Diego. We work in a fast-paced environment and have a lot of challenges to solve. If you like to work in a huge scale environment and want to help us build products that have a huge impact on the industry, and the web - then your place is with us.
What you will do:
Develop and improve models that analyze millions of videos and images every day across the web, Smart TVs, YouTube, Facebook, Twitter, Instagram, TikTok and more to detect the content categories they are about.
Work alongside experienced data scientists and engineers in a cutting-edge environment, contributing to advanced ensembles of models at huge scale.
Participate in the full development cycle - from research and experimentation through to deployment - gaining hands-on experience with production ML systems.
Leverage AI-powered tools and assistants as part of your daily workflow to accelerate research, coding, and analysis.
Help advertisers avoid negative or irrelevant content and target what's most relevant to their brand, keeping the web free for everyone.

We are seeking a Package Layout Design Engineer to join our hardware team and contribute to the physical design of advanced IC packages for next-generation machine learning and data center ASICs.
In this role, you will execute package layout tasks from floor planning through tape out and manufacturing release, working closely with senior engineers, SI/PI, thermal, and manufacturing teams to deliver production-ready designs that meet performance, density, and reliability targets.

Key job responsibilities
- Execute package layout tasks across the design cycle: die floor planning, bump/pad assignment, RDL routing, substrate design, verification, and tape out release.
- Implement physical designs for advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB, or similar).
- Support package floorplan development considering die placement, bump maps, power/ground distribution, signal escape routing, and decoupling capacitor placement.
- Perform RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi-layer organic substrates or silicon interposers.
- Support die-level RDL routing and bump planning in coordination with ASIC physical design teams to help co-optimize the die-package interface.
- Contribute to cross-level layout co-optimization across die RDL, interposer/substrate, and PCB levels under guidance from senior engineers.
- Assist in maintaining package stack-up definitions in collaboration with SI/PI and materials engineering teams.
- Run physical verification checks (DRC, connectivity, shorts/opens) and support design closure.
- Follow and help refine package design rules and guidelines, working with OSAT partners and foundries to ensure DFM compliance.
- Collaborate with SI/PI engineers to incorporate electrical constraints into the physical layout - impedance-controlled routing, power plane optimization, and critical net shielding.

We are looking for a Nitro System Manufacturing Integration Lead Engineer to be part of defining, shaping, and implementing manufacturing flows, test definitions, and card-to-server integration processes for Nitro-based platforms. This includes to be part of the manufacturing flow architecture, production test strategy, process stabilization, and yield optimization bridging system design intent with high-volume manufacturing execution.

Key job responsibilities
As a System Manufacturing Integration Lead Engineer, in the Nitro team, you will own the end-to-end manufacturing flows for accelerator card-to-server integration across manufacturing partner facilities driving the process from initial definition through stabilization into a scalable, high-yield mass production operation.

Key responsibilities include:
- Architect manufacturing flows - be part of the complete card-to-server integration sequence, including every process step, quality gate, and decision point from sub-assembly through system integration and tests.
- Define test strategy - be part of determining what to test, when, and at which station, covering card-level functional tests, post-integration validation, firmware provisioning, and first power-up diagnostics.
- Establish classification criteria - be part of determining pass/fail thresholds and test exit gates to maximize yield and minimize material waste.
- Drive process stabilization - work directly and on-site with manufacturing partners to implement, debug, and iterate on manufacturing flows from early builds through a locked, repeatable production process.
- Design alternative flows - develop parallel manufacturing paths to address real-world constraints such as component availability gaps, deferred card integration, and hub-based assembly models.
- Own process documentation & KPIs - maintain manufacturing flow baselines, drive process change control, and track yield, first-pass rate, cycle time, and defect Pareto.
- Lead cross-functional coordination - serve as the single point of ownership across hardware engineering, firmware, test/vetting, thermal, mechanical, and operations teams for Nitro-based accelerator servers built at scale.

We're looking for Electrical Engineering graduates to join the Pre-Silicon Verification Team based in Haifa.

As a Junior Pre-Silicon Verification Engineer, you'll work at the heart of chip development, collaborating across teams to ensure our semiconductor platforms meet the highest standards before they reach production.
IO verification team will expose you to the most advanced technologies , as we lead the market with our leaving devices - youll soon have to expertise most advance protocols

A day in the life
In this role, you'll engage in pre-silicon verification work that connects every phase of our product development journey- from initial product definition through firmware and software development.
You'll collaborate with hardware designers, software engineers, and cross-functional teams to validate complex semiconductor architectures and protocols.
Your days might include developing and executing verification test plans, analyzing simulation results, troubleshooting design issues, and participating in design reviews.
You'll work with advanced verification methodologies and tools, gaining exposure to cutting-edge technologies that define the next generation of cloud infrastructure.

We're looking for exceptional engineers to join our Signal/Power-Integrity and Packaging team. A team that sits where the Silicon meets the Board, bridging the gap between what happens internally at the DIE and the overall system interconnect and the external memories and peer devices.
What sets us apart:
Small team, yet a one stop shop for IP electrical integration at the DIE level, Package design, SI/PI simulations, Layout, Board-design and advanced lab characterization.
Combining Signal-Integrity and Layout, to come up with optimized Package and PCB designs.
Holistic view of the entire interconnect, from the DIEs metals, through the Package, to the PCB traces, and all the way to the peer device.
In-depth post-silicon characterization, using advanced measurement techniques, far exceeding traditional compliance measurements.
Deep dive mentality, in both theory and the bolts and nuts that make the internal circuitry of the electrical interfaces.

The SIP (Signal-Integrity & Packaging) team is part of Annapurna-Labs Chip development team.
The team is dealing with the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
The teams work includes close work with the BackEnd team on integrating these interfaces to the Die, the package layout design of the BGAs substrate, Signal and power integrity simulations, and working with the system team to come up with optimal pin-out and optimal PCB breakout schemes.
We are looking for highly motivated Electrical Engineering graduates, or engineers with up to 3 years' experience in related fields, to join our growing team specializing in Signal Integrity and IC Package Design. The position offers a unique entry point into a diverse and multidisciplinary domain.

Key job responsibilities
Work on advanced high-speed interfaces such as PCIe, DDR and Ethernet.
End-to-end solution of high-speed interfaces; from floor-planning at the DIE level, through Package and PCB routing, addressing both robust SI/PI considerations as well as optimizing layout routing.
Signal and power integrity modeling and simulation of high-speed interconnects using advanced SI/PI simulation tools.

We're looking for exceptional engineers to join our Signal/Power-Integrity and Packaging team. A team that sits where the Silicon meets the Board, bridging the gap between what happens internally at the DIE and the overall system interconnect and the external memories and peer devices.
What sets us apart:
Small team, yet a one stop shop for IP electrical integration at the DIE level, Package design, SI/PI simulations, Layout, Board-design and advanced lab characterization.
Combining Signal-Integrity and Layout, to come up with optimized Package and PCB designs.
Holistic view of the entire interconnect, from the DIEs metals, through the Package, to the PCB traces, and all the way to the peer device.
In-depth post-silicon characterization, using advanced measurement techniques, far exceeding traditional compliance measurements.
Deep dive mentality, in both theory and the bolts and nuts that make the internal circuitry of the electrical interfaces.

The SIP (Signal-Integrity & Packaging) team is part of Annapurna-Labs Chip development team.
The team is dealing with the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
The teams work includes close work with the BackEnd team on integrating these interfaces to the Die, the package layout design of the BGAs substrate, Signal and power integrity simulations, and working with the system team to come up with optimal pin-out and optimal PCB breakout schemes.

As a SIP team member, you will assume responsibility for all electrical aspects of physical interfaces of advanced I/Os, PLL, Memory and SerDes interfaces, from integration at the Die level, through SI/PI simulation and package layout, to reference board design aspects.

This position is for an experienced engineer with strong background in high-speed electrical interfaces, such as DRAM, PCIe, Ethernet SerDeses. The line of work is multi-disciplinary, combining Package-Design, Back-End integration of electrical IPs, SI/PI extractions & simulations.


Key job responsibilities
Deep dive into electrical IPs, integrated into the DIE;
I/O ring design and close work with Backend team on floor-planning all I/O interfaces at the DIE level.
Lead test studies of Die bump-out arrangements and Package substrate breakout.
Lead layout test studies of package pin-out arrangements and PCB board breakout.
Design large and complex package substrates.
Carry advanced SI/PI extractions and simulations to validate the design from the silicon to the peer device at the board level.

We are looking for an energetic, detail-oriented individual to join our Data Center Engineering Operations Team. This committed group works to maintain the critical physical infrastructure that supports Amazon Web Services. Specifically, this team works to ensure that the data center's MEP operates at 100% availability while maintaining first-class customer service to the teams and groups within the data centers.
The Data Center Engineering Operations Facility Engineer is responsible for operating and maintaining all electrical, mechanical, and fire/life safety equipment within the data center. This person serves as a technical resource to support Amazon within its owned and operated data centers. Data center equipment that supports mission-critical servers must maintain better than 99.999% uptime. DCEO Facility Engineers are also tasked with driving innovation while reducing operational costs in the facilities.

DCEO Facility Engineers are Amazons front line responders for hands-on electrical and mechanical equipment troubleshooting and operation. This equipment includes, but is not limited to, stand-by diesel generators, switchgear, UPSs, PDUs, AHUs, chillers, cooling towers, chemical treatment systems, pumps, motors, VFDs, and building automation systems.


Key job responsibilities
- Operate and maintain mechanical and electrical equipment.
- Perform root cause analysis of equipment failures.
- Troubleshooting of facility and rack-level events within internal SLA.
- Ensure all safety procedures are adhered to while performing work.
- Able to work shifts (rotating work days during the weeks).
- Take daily operational readings of all mechanical and electrical equipment.
- Utilize internal CMMS to manage building workflows.

We are developing leading edge products, manufactured on leading edge technologies. We offer a dynamic, open, teamwork environment operating at high pace mode.

Key job responsibilities
Primary responsibilities:
- Development of DfX (DfM, DfT, DfQ&R, etc.) methodologies and BKMs (Best Known Methods).
- DfX activities during the product design stage.
- Product quality & reliability validation (QRV) and ongoing quality & reliability monitoring (OQRM).
- Q&R engineering of volume manufacturing: auditing, monitoring, risk assessment and disposition of non-conformance events/non-conforming material, defining and implementing corrective actions.
- RMAs: investigation, disposition, reporting and follow-up.

We are developing leading edge products, manufactured on leading edge technologies.
We offer a dynamic, open, teamwork environment operating at high pace mode.

Key job responsibilities
Assume full ownership of mechanical and thermal design of Annapurna ICs.
Engage with product architect and design teams on future products package and assembly needs
Perform package level thermal simulations.
Perform package level mechanical simulations.
Lead and design thermal and mechanical measurements of ICs.
Explore and provide recommendations on both available and future packaging and assembly technologies for Annapurnas products.
Engage with substrate and assembly vendors on future technologies roadmap.
In collaboration with HW Dev team optimize mechanical vs. thermal tradeoffs.
Ensure testability of the ICs in collaboration with Test Engineer team.

As a Software Development Engineer in Test on our team, you will own the quality of Nitro card embedded software and firmware. You will design, develop, and maintain test automation for embedded systems and components, covering hardware interface verification, real-time firmware behavior validation, firmware update integrity, and fleet-scale deployment confidence. You will collaborate closely with firmware development teams to troubleshoot complex system-level problems at the hardware-software boundary and ensure timely delivery of high-quality Nitro card software to AWS Cloud solutions.

Key job responsibilities
- Own the firmware test automation framework - architect, develop, and extend a Python-based validation solution that scales across multiple Nitro card generations and hardware platforms, automating test coverage across the full firmware stack from boot sequences through board management layers and card-level system integration.
- Design and implement traceable, specification-driven test cases that validate firmware functional correctness, fault tolerance, and performance across hardware components, communication interfaces, and cross-subsystem interactions.
- Optimize CI/CD pipelines by integrating pre-merge and post-merge firmware validation, defining trigger policies per hardware generation, enforcing coding-standard compliance, and reducing commit-to-validated cycle time.
- Troubleshoot complex embedded system failures by analyzing firmware logs, system traces, and hardware diagnostics, then translate field incidents into targeted regression suites that prevent recurrence.
- Collaborate with firmware and hardware teams during new-generation silicon bring-up, define test plans, drive quality gates for production release, and mentor teammates on testing best practices and system architecture.

A day in the life
You start your morning reviewing overnight CI results and triaging any firmware validation failures flagged across active Nitro card generations. Mid-morning, you pair with a firmware engineer to debug a boot-sequence regression discovered during pre-merge testing, using hardware-in-the-loop test benches and system traces. After lunch, you join a design review for a next-generation Nitro card, providing input on testability and proposing validation strategies for new subsystem interfaces. Later, you refine your test framework to improve coverage for a recently released feature, then wrap up by sharing your findings in a team knowledge-sharing session.

We are looking for talented engineers to help us develop the semiconductor platform which is based on revolutionary architecture.
Take part in the development of cutting edge products within disruptive system architecture. Youll have the opportunity to work on the technologies that power the worlds largest Cloud provider, within a dynamic, open, and fast-paced environment. Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world.

Exciting opportunity to join Amazon in developing its next generation products for the cloud market.
We are looking for talented people to join the team and help us technically lead the challenges of the next decade.
In this job you will be exposed and learn wide range of expertise such as: C++ programing, hardware design, data mining, Verilog simulations, working with various high end test equipment and more
If paving new roads on edge of technology within a strong and vibrant team is what you seek, your place is with us.