דרושים » ייצור ותעשייה » NPI & System Product Engineer

We are seeking a senior ATE Software Engineer to design, build, and deploy our next-generation automated manufacturing test platform for advanced telecom, high-density switching, and optical networking hardware.
In this role, you will bridge the gap between R&D hardware/firmware teams and high-volume manufacturing lines. You will take ownership of ingesting, refactoring, and consolidating disparate R&D scripts, diagnostic tools, and legacy software into a single, scalable, production-grade test platform.
We expect you to leverage modern AI-assisted development tools and workflows to maximize engineering efficiency, accelerate delivery timelines, and build highly robust, self-healing test automation. You will deploy test stations across global Contract Manufacturers (EMS/ODM), actively stabilize production lines through bring-up and ramp-up, and drive continuous test maintenance and root-cause failure analysis (RCA).
Key Responsibilities
Test Platform Architecture & Software Development:
Design, develop, and productize robust, modular test software frameworks for board-level (PCBA) and system-level manufacturing testing across multiple product lines and manufacturing sites.
Codebase Unification & Refactoring:
Consolidate and standardize R&D diagnostic libraries, silicon validation scripts, and firmware tools developed across various environments (Python, C# / Visual Studio, VB, ATEasy, Linux) into a unified, maintainable test execution engine.
AI-Accelerated Development & Workflow Automation:
Actively integrate Generative AI tools and AI coding agents into your daily workflow to accelerate code conversion/refactoring, automate test case synthesis, generate edge-case validation scripts, and enhance overall codebase resilience.
Production Line Deployment & Stabilization:
Deploy test stations and fixtures to local and overseas EMS/CM production lines. Monitor, debug, and fine-tune test execution during NPI and ramp-up phases until yield, takt time, and test stability targets (CPK / First Pass Yield) are achieved.
Failure Investigation & Intelligent RCA:
Investigate complex system-level and component-level test failures. Utilize advanced log analysis, structured telemetry, and pattern recognition to drive root-cause investigations and implement preventive software/hardware fixes.
Ongoing Test Maintenance & Optimization:
Provide continuous operational Production line support and maintenance, bug fixes, software updates, and station cycle-time optimizations for active mass-production lines.
R&D Collaboration & Test Specification:
Collaborate closely with Hardware, Firmware, and Validation teams during early design phases to define test specifications, drive Design for Testability,
Documentation & Technical Reporting:
Author and maintain comprehensive testing documentation, Standard Operating Procedures (SOPs), test coverage matrices, and detailed failure analysis reports.

we are seeking a highly motivated Power Integrity Engineer to join our Hardware Engineering team. In this role, you will be responsible for defining, analyzing, simulating, and validating power delivery networks (PDNs) for next-generation networking platforms supporting high-performance ASICs, advanced SerDes interfaces, optical modules, and AI-scale networking systems.
You will work closely with hardware architects, PCB designers, ASIC teams, signal integrity engineers, mechanical engineers, and manufacturing partners to ensure robust power delivery, optimal system performance, and successful product deployment.
Responsibilities
Lead Power Integrity (PI) activities throughout the hardware development lifecycle, from architecture through production.
Define and optimize board-level and package-level Power Delivery Networks (PDNs) for high-current networking ASICs and supporting devices.
Perform pre-layout and post-layout PI simulations using industry-standard tools.
Establish target impedance requirements and validate compliance across all power rails.
Analyze DC voltage drop, AC impedance, transient response, and power distribution performance.
Collaborate with PCB layout engineers to optimize stackups, plane structures, decoupling strategies, and power routing.
Work closely with Signal Integrity engineers to ensure SI/PI co-optimization of high-speed interfaces.
Develop power integrity design guidelines and best practices for next-generation networking products.
Support schematic reviews, layout reviews, and design sign-off activities.
Perform laboratory measurements and correlation using oscilloscopes, VNAs, power analyzers, current probes, and related equipment.
Investigate and resolve PI-related issues during board bring-up, validation, and production.
Collaborate with ASIC, FPGA, memory, optics, and power component vendors to optimize overall system performance.
Drive continuous improvement of PI methodologies, simulation flows, and validation processes.

we are looking for a senior software system architect to join the team shaping networking management systems, aiops platforms, and applied ai solutions for ai cluster operations. you will work with customers, internal operational teams, fellow architects, product, and engineering teams to translate sophisticated operational challenges into clear requirements and scalable architectures, and carry these capabilities through implementation and delivery into products that deliver measurable value for customers.
we seek someone with deep technical judgment, a broad system perspective, and the persistence to move ideas into production-someone who asks sharp questions, catches consequential details, and builds alignment across teams.
what you'll be doing:
define architectures for management and intelligent automation capabilities spanning telemetry, observability, remediation, and operational automation.
engage customers, cluster operations teams, and compute authorities to understand their challenges and architect solutions that improve operational efficiency, reliability, and scalability.
partner with product and engineering to translate architectural recommendations into prioritized features and drive their inclusion in the plan of record (por), defining requirements, dependencies, and success criteria.
resolve system tradeoffs across hardware, firmware, software, and data platforms, with attention to scale, reliability, performance, and usability.
guide design decisions through implementation, with hands-on development of targeted proofs of concept (pocs) and technical investigations as needed to validate critical assumptions.
offer strategic direction and system -level leadership throughout teams, guiding engineering choices and promoting sophisticated, ai-centered operating practices.

what if your Python automation caught a critical asic bug before the physical silicon was even manufactured? our simulation platforms make that happen every release cycle! we are the system ethernet QA team at our r&d center, responsible for the testing and qualification of virtual networking silicon (simx) and software-from l2 forwarding and l3 routing to overlays, qos, and security. with simx, developers and QA engineers get hardware-free, early access to the asic for better debugging.
we are looking for a senior QA software engineer who combines network protocol expertise with strong Python automation skills. does debugging a bgp evpn route leak excite you as much as refactoring a TEST framework? then we should talk!
what you'll be doing:
we don't just complete checklists; we collaborate closely with r&d to lead the quality of new features from design to deployment. in this role, we:
review architectural designs and requirements for new features introduced to the product
drive the design, development, and execution of tests across functional, performance, and security scopes as part of sw ga and update releases
develop Python automation suites built on clean oop principles
chase down defects and validate fixes until we fully resolve the root cause
leverage the simx platform to validate code and debug the asic long before hardware arrives

we have been elevating computer graphics, pc gaming, and accelerated computing for more than 25 years. today, we're tapping into the unlimited potential of ai to define the next era of computing. as a member of our team, you'll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. come join the team and see how you can make a lasting impact on the most groundbreaking technologies.
our networking bu group is seeking to hire an expert firmware design engineer for the ethernet switch firmware core team. the next generation of switches are a crucial component of the most innovative ai and cloud computing networks in the world. as a member of the ethernet firmware team, you will craft and develop the firmware abstraction layer in the eth switch. this role will require you to participate in the design & development of firmware while working closely with hardware and architecture team to ensure timely delivery of our products to the market.
what you'll be doing:
highly involved in the entire software development process from architecture to integration testing of firmware for the spectrum asic product line.
work with hw & asic team to provide insights into developing the next gen of the groundbreaking of silicon and systems.
design and implement algorithms to improve system scale and performance.
work with higher layer software teams to debug issues reported by customers (internal and external).
design, implement and integrate new features according to the product roadmap.
have a new insight on how to improve our software? why not! bring your ideas to life by innovating during our hackathons
collaborate with other r&d teams around the globe.

We are seeking a highly skilled and experienced multidisciplinary engineer with a strong background in system design to join our team. In this role, you will contribute to our upcoming projects and play a key part in the rapid expansion of the Ethernet market.
As a such, you will be responsible for developing high-speed digital and analog circuit boards used in Ethernet products. Your duties will include designing board schematics, overseeing PCB layout, and conducting lab . Additionally, you will be responsible for evaluating new hardware solutions, providing technical leadership in troubleshooting and reviewing schematics, layouts, and design for manufacturability (DFM), as well as managing components selection.

job overview:
join our gpu hardware verification team in raanana, israel, and help shape the future of the world's most widely deployed gpu architecture - mali. as a staff hardware Verification engineer, you will play a key technical role in verifying advanced gpu components and subsystems, working alongside architects, designers and Verification engineers to deliver high-quality, industry-leading graphics technology. you'll contribute to complex verification environments, solve challenging technical problems and help drive continuous improvements to our verification methodologies and flows.
responsibilities:
develop and execute verification plans for advanced gpu components and subsystems.
develop and maintain ai tools, agents, and skills to support our engineering teams and workflows.
build, maintain and enhance robust verification environments using systemverilog and uvm.
apply coverage-driven, constrained-random and, where appropriate, formal verification techniques to achieve comprehensive functional coverage.
debug complex functional issues and work closely with design and architecture teams to identify and resolve root causes.
contribute to block-level and system -level verification, including environment integration and regression analysis.
improve verification methodologies, automation, scripting and continuous integration flows to increase quality and efficiency.
participate in verification reviews and support verification sign-off activities.
share technical knowledge and collaborate with colleagues across the wider gpu engineering organisation.

We are looking for an experienced Senior Signal Integrity Engineer to join our Hardware Engineering team. This role focuses on ensuring optimal signal integrity for high-speed interfaces, including Ethernet, PCIe, DDR5, and other next-generation technologies. As part of the team, you will be responsible for performing signal integrity analysis, developing signal integrity models, and ensuring electrical compliance for high-speed SERDES I/Os.
Responsibilities:
Conduct signal integrity analysis and simulations for high-speed interfaces such as 112Gbps Ethernet, PCIe Gen5, and DDR5 interfaces.
Develop and implement signal integrity guidelines for PCB design, ensuring high-performance and low-loss signal paths.
Analyze and resolve signal integrity issues related to high-speed interfaces, including reflection, crosstalk, and power delivery network (PDN) issues.
Collaborate with PCB layout engineers to optimize design for signal integrity, ensuring compliance with electrical standards and high-speed design best practices.
Perform time-domain and frequency-domain analysis, including loss, jitter, and eye-diagram analysis.
Utilize EDA tools such as Ansys SIWAVE, HFSS, or similar for simulation and validation of signal integrity designs.
Work closely with cross-functional teams to integrate signal integrity considerations into the overall hardware design process.
Develop behavioural models based on measured signal integrity data to inform future design and simulation work.
Conduct pre- and post-layout simulations and measurements for high-speed signal interfaces.

The AI VLSI department develops top notch NPU that enables the execution of state-of-the-art LLMs, Generative AI models, and neural networks with exceptional performance, impacting multiple hardware and software teams across the company facing amazing PPAA challenges of the edge market.
In this role, as VLSI Team Leader in the AI VLSI department, you will lead a team of engineers developing cutting edge VLSI products such as - DSP, HW accelerators and AI Processors for the edge market, with full responsibility on the Front-End Design.
You will drive the development of robust, scalable, and efficient VLSI design, working closely with global Architecture, hardware simulator and Software teams to shape our companys next generation of AI solutions.
We are looking for an exceptional hands-on leader with strong technical expertise, proven experience leading VLSI Front-End Design engineers, and a track record of delivering complex, state-of-the-art products on time and in production ready quality.
The ideal candidate is execution-driven, innovative, and passionate about building high-performing team and cutting-edge AI technology.
Responsibilities
Manage and lead a team of Front-End Design engineers.
Be accountable for the teams development lifecycle, including architecture, development, validation, and release, focusing on meeting PPAA targets.
Lead development of advanced VLSI IPs for AI processors, DSP and HW accelerators while continuing pushing the VLSI design methodologies, procedures, sign off and AI tools assimilation to its next level.
Support system bring-up, debugging, and customer-facing activities when needed.

As a Wireless Platform Architect, you will play a key role in defining the architecture of our company's next-generation Radio Subsystem (RSS) platforms for wireless technologies including Wi-Fi, Bluetooth and UWB. You will take end-to-end responsibility on the system-level architecture of a complete wireless communication subsystem, including system spec, requirements for implementation teams, definition of interfaces and testing concept.
You will work closely with multidisciplinary development teams and directly with customers, from early system architecture and trade-off analysis through implementation, integration, validation and productization.
Responsibilities:
Define the RSS end-to-end architecture and HW/SW partitioning, including interfaces between the radio, PHY, MAC, CPU/MCU, memories, PMU, clock and reset management (CRM) and other subsystem components.
Define architecture and operational mechanisms for multi-protocol operation and interoperability, including HW interfaces, state machines, control flows and operation sequences.
Define sleep/wake-up modes, testability, security and debug.
Drive PPA optimization and competitive benchmarking of the RSS, with particular focus on low-power operation, silicon area and overall system efficiency.
Work closely with RF, PHY/algorithm, HW, SW/firmware, verification and integration teams, from early system studies and architecture definition through RTL/FPGA validation and system bring-up.
Work directly with customers during technical engagements to define the RSS integration into their SoC and support customers throughout SoC integration, validation and productization, addressing system-level architecture, interoperability and integration challenges.