דרושים » חשמל ואלקטרוניקה » AI Research Engineer - Chip Design

As a member of our ML group, you will design, prototype, and ship agentic GenAI systems used by chip design engineers to accelerate their day-to-day workflows. We are looking for a machine learning engineer who is energized by taking LLMs from "promising demo" to "depended-on tool": designing the agent loops, retrieval pipelines, and evaluation frameworks that make this transition real. Success in this role means agents that meaningfully shift how our customer teams work, backed by measurements you trust.

You will join a growing team of ML and software engineers building GenAI solutions for chip design teams. In this role, you will:

Design and build agentic systems featuring multi-agent coordination, long-horizon reasoning, tool use, and planning frameworks.
Develop end-to-end solutions, including domain-specific agents and high-performance retrieval pipelines spanning diverse data sources.
Partner with subject-matter experts on the customer teams to translate their workflows and rules of thumb into concrete agent assignments, prompts, tools, and guidelines.
Build the evaluation backbone for our agents: define success measures, curate offline golden sets, and instrument online telemetry to power feedback loops that drive fast, safe iteration with real cost and quality control.
Drive prompt engineering, model selection, and lightweight model adaptation as the workloads demand.
Collaborate closely with software engineers on the team to productionize your work, and with researchers and customers to shape what we build next.
Stay current with the rapidly evolving agentic and LLM landscape and bring promising techniques into our products with good engineering judgment.

We are seeking a creative and hands-on Deep Learning Research Engineer to drive model and architecture innovation across our sensing platforms. In this role, you will go beyond off-the-shelf models, exploring novel neural network designs, designing rigorous training and validation pipelines, and translating inventive concepts into clean, high-performance implementations. While our domain deals with physical data, this is an ML-first role: we are looking for a deep learning specialist with strong research intuition, expertise in PyTorch, and the drive to solve non-standard, real-world problems.

Responsibilities
Conceive, design, and implement novel neural network architectures tailored for complex physical sensing, reconstruction, and inverse problems.
Lead end-to-end hands-on research: data preparation, model formulation, training, hyperparameter exploration, and failure-mode analysis.
Build, train, and rigorously validate deep learning models using Python and PyTorch.
Formulate custom loss functions, regularization techniques, and inductive biases that capture domain-specific constraints.
Design comprehensive validation and benchmarking suites to stress-test model robustness, generalization, and scaling behavior.
Propose creative, non-conventional modeling ideas, stay abreast of state-of-the-art DL literature, and rapidly prototype proof-of-concepts.
Collaborate cross-functionally with physicists and optical software engineers to benchmark models against simulated and experimental lab datasets.

Required Power and Signal Integrity Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
You'll set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners.
The ML, Systems, & Cloud AI (MSCA) organization designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all services (Search, YouTube, etc.) and Cloud.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities:
Design and optimize power distribution networks (PDN) across chip, package, and board levels. This includes managing power/ground planes, decoupling capacitors, and power gating strategies.
Conduct both pre-layout and post-layout power integrity simulations to analyze power and ground noise (SSN/SSO), voltage drops (IR drop), and electromagnetic interference (EMI).
Implement and verify low-power design methodologies, such as multi-voltage designs and clock gating, using power intent formats like UPF/CPF.
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR), Spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.

We are seeking an experienced Signal/Image Processing and Machine Learning engineer to join our team. The role focuses on developing innovative, real-time deep learning and signal processing solutions for new sensing and imaging systems, including video restoration. You will be part of an interdisciplinary team developing technologies that will shape future Apple products.
Description
Algorithm and model development:
- Design, implement, and optimize signal processing and machine learning models for sensing and imaging tasks, including video restoration.
- Develop and validate models using real sensor data, simulated data, and public datasets.
- Prepare, filter, process, and analyze large-scale datasets to train and evaluate models.
- Analyze your algorithm's results and benchmark them against leading methods, and theoretical bounds.
- Optimize models for real-time performance, low latency, and resource efficiency on-device.

Sensing and research:
- Develop algorithms that combine classical signal processing with learned models to extract robust information from sensor data.
- Investigate efficient architecture patterns (lightweight backbones, attention mechanisms, recurrent designs) suitable for real-time, on-device inference.
- Explore how algorithmic approaches can mitigate artifacts and limitations of new sensing and imaging systems.
- Stay current with recent advances in signal processing, computer vision, and machine learning.

Collaboration and technical leadership:
- Work closely with ML researchers, SW, HW, sensor, and architecture engineers to translate research ideas into robust models and practical, shipping systems.
- Provide technical guidance and mentorship to junior engineers, and help shape the team's technical direction.

Responsibilities
- Own the end-to-end development of real-time algorithms, from concept and prototyping through validation and deployment.
- Define evaluation methodology, metrics, and failure analysis processes for sensing and imaging algorithms.
- Drive trade-off decisions among accuracy, latency, power, and memory across algorithm, HW, and system constraints.

We are seeking an experienced Signal/Image Processing and Machine Learning engineer to join our team. The role focuses on developing innovative, real-time deep learning and signal processing solutions for new sensing and imaging systems, including video restoration. You will be part of an interdisciplinary team developing technologies that will shape future Apple products.
Description
Algorithm and model development:
- Design, implement, and optimize signal processing and machine learning models for sensing and imaging tasks, including video restoration.
- Develop and validate models using real sensor data, simulated data, and public datasets.
- Prepare, filter, process, and analyze large-scale datasets to train and evaluate models.
- Analyze your algorithm's results and benchmark them against leading methods, and theoretical bounds.
- Optimize models for real-time performance, low latency, and resource efficiency on-device.

Sensing and research:
- Develop algorithms that combine classical signal processing with learned models to extract robust information from sensor data.
- Investigate efficient architecture patterns (lightweight backbones, attention mechanisms, recurrent designs) suitable for real-time, on-device inference.
- Explore how algorithmic approaches can mitigate artifacts and limitations of new sensing and imaging systems.
- Stay current with recent advances in signal processing, computer vision, and machine learning.

Collaboration and technical leadership:
- Work closely with ML researchers, SW, HW, sensor, and architecture engineers to translate research ideas into robust models and practical, shipping systems.
- Provide technical guidance and mentorship to junior engineers, and help shape the team's technical direction.

Responsibilities
- Own the end-to-end development of real-time algorithms, from concept and prototyping through validation and deployment.
- Define evaluation methodology, metrics, and failure analysis processes for sensing and imaging algorithms.
- Drive trade-off decisions among accuracy, latency, power, and memory across algorithm, HW, and system constraints.

Requied Full Chip CAD Physical Design Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The AI and Infrastructure team is redefining whats possible.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Demonstrate an understanding of the Register-Transfer Level (RTL) to Graphic Data Stream (GDS) II flow.
Manage the implementation of large, complex system-on-chips (SoCs), subsystems, and sub-wrappers, and demonstrate an understanding of associated issues and solutions.
Utilize floorplanning, power grid design, and place-and-route methodologies, and use Synopsys tools like Floorplan Compiler (FC) and Formality.
Exhibit an understanding of advanced node design (e.g., 5nm and below) and related optimization techniques.
Develop script in Synopsys TCL and Python.

Required Wafer-Scale System: Computation (LLM) and Communication (NoC) Co-Design
In this job opening, we are seeking a highly motivated and visionary researcher to join our team focused on chiplet-based computing systems. This role involves research and development in chiplet-based architectures, aiming to overcome performance and scalability limits of traditional compute platforms.
Responsibilities:
Conduct cutting-edge research on the co-design of communication and computation for wafer-scale systems. On the communication side, the work focuses on architecting Networks-on-Chip, providing scalable, high-bandwidth, and ultra-low-latency interconnects that efficiently span multiple dies and support fine-grained data movement. On the computation side, the research emphasizes optimizing and mapping training and inference workloads to fully exploit wafer-scale resources, improving performance, scalability, and energy efficiency through intelligent task placement and scheduling.
Investigate various aspects of system design, including:
Network-on-Chip design, further including Topology exploration, routing algorithms, and protocol/flow-control design to support high-throughput collective communication, low-latency synchronization, and efficient model/data parallelism
Expressing and Mapping LLM Parallelism to Wafer-Scale System that simplify LLM parallelism (e.g., tensor, pipeline, and data parallelism) and efficiently map training and inference workloads onto wafer-scale system.

Required Design AI Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Lead an edge AI IP design team including definition, implementation and deployment, and define IP development methodologies sharing unified blocks within the IP design team.
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Demonstrate technical involvement throughout the entire Intellectual Property (IP) development cycle, ensuring seamless integration into System-on-Chip (SoC).
Perform RTL development (e.g., coding and debug in SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Collaborate closely with software, verification, emulation, physical design, packaging, and silicon validation stakeholders to ensure that designs are complete, correct, and performant.

Required Design Engineer, Edge AI, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing robust, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our platforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Lead a complex ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

Required Senior SOC and IP Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.