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Requied Full Chip CAD Physical Design Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The AI and Infrastructure team is redefining whats possible.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Demonstrate an understanding of the Register-Transfer Level (RTL) to Graphic Data Stream (GDS) II flow.
Manage the implementation of large, complex system-on-chips (SoCs), subsystems, and sub-wrappers, and demonstrate an understanding of associated issues and solutions.
Utilize floorplanning, power grid design, and place-and-route methodologies, and use Synopsys tools like Floorplan Compiler (FC) and Formality.
Exhibit an understanding of advanced node design (e.g., 5nm and below) and related optimization techniques.
Develop script in Synopsys TCL and Python.

Required Senior SoC Formal Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to build the best cloud in the world for our services and for our Cloud customers, by solving real world business issues of performance, cost, and scale, utilizing hardware, software, and system solutions. To better serve evolving cloud needs, we are establishing a team in Israel to develop custom chips for servers.
In this role, you will perform formal verification of design properties of complex ASIC designs. You will collaborate closely with design and verification engineers to define meaningful properties that capture the design intent of a logic block and constraints on its input stimulus. You will also help define and improve design and verification methodologies that allow you to achieve formal verification closure.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Plan the formal verification strategy and create the properties and constraints for complex digital design blocks.
Utilize formal property verification tools combined with formal verification closure techniques to verify properties and apply sign-off to blocks.
Pioneer and refine formal verification methodologies by systematically embedding AI tools to optimize verification accuracy.
Architect and implement reusable formal verification components.

Required Senior Silicon DFT Lead
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

Required CPU Design for Test Engineer, Cloud
About the job
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our platforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
In this role, you will be part of a varied team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design-for-Test (DFT) Engineer, you will play a crucial role in DFT design, and support devices of extreme complexity to production. You will be responsible for developing flows, automation, and methodology, executing DFT activities. You will be responsible for test vectors end-to-end, from generating DFT content on complex design, debugging to coverage goals, simulating it at gate level, sign-off DFT to tapeout, and debugging Si results.
Responsibilities:
Execute activities in the design, implementation, and verification of Design for Testing solutions for Application-Specific Integrated Circuit (ASICs).
Develop DFT strategy for array DFT, hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).
Perform ATPG, scan coverage debug and drive design fixes for coverage and quality improvements.
Perform DFT verification at RTL and gate level.
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT design requirements are met and mutual dependencies are managed.

We are looking for a talented Algorithm Engineer to join our team and help shape the next generation of products.

In this role, you will develop and optimize algorithms for database operations running on our hardware accelerator, improve performance, and enable new capabilities.

You will gain a deep understanding of the entire stack from systems and applications to software and hardware and work across different parts of the codebase.

Responsibilities:

Researching state-of-the-art algorithms and techniques for data analytics and hardware acceleration

Implementing these algorithms in software, then simulating and optimizing their performance

Working closely with software and hardware engineers

Participating in design reviews and contributing to key design decisions

Required Senior Silicon Physical Design Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.

We are looking for an experienced Software Engineer (4+ years) to join the team as an AI Integration Engineer, supporting one of our enterprise clients as part of their AI-Native Development program.
In this role, you will act as an AI Champion and Technical Mentor within the clients R&D organization. Your mission is to help development teams effectively integrate AI tools, agentic coding workflows, and best practices into their daily software development lifecycle (SDLC). You will help guide teams through AI adoption, help overcome resistance, and ensure AI delivers real value.
This is not a feature-delivery or coding-focused role, especially in the early stages, the position is centered on enablement, training, and integration, working closely with teams to embed AI development tools into real workflows and support the organizations AI transformation.
This is a high-impact role focused on technical enablement, AI expertise, and effective collaboration with development teams, and intended for experienced engineers who actively use AI in their day-to-day development work and are looking to influence how teams work, rather than for junior profiles or engineers seeking a purely coding-focused position
What Youll Do:
Help drive adoption and optimization of Claude Code and/or similar Agentic coding tools
Support software and QA engineers, answer technical questions and help unblock teams
Stay on the cutting edge of AI releases and best practices, turn your learnings into shareable assets (custom rules, agents, skills, demos, playbooks, etc.)
Measure impact, identify gaps and improvement opportunities across the SDLC
Help defuse resistance to change with patience and empathy
Partner with DevOps, architects and management to track and optimize AI utilization.

Required Signal/Power Integrity Engineer, PhD Graduate
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities:
Simulate high speed interface electrical behavior using HSPICE or other circuit simulators.
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Collaborate extensively with cross-functional teams, including ASIC architects, digital/analog designers, physical design/layout engineers, and system engineers, to define specifications and resolve integration challenges.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR) , Spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.
Establish robust design rules and guidelines for optimal signal/power integrity during PCB and package layout, ensuring high production yield and reliability.

Were expanding a fast-growing practice that helps engineering teams leverage AI in their SW development lifecycle and transform into AI-native teams. Weve served dozens of satisfied customers in Israel and abroad and are now hiring a hands-on engineer to lead and drive R&D AI transformation programs, AI tooling adoption & tracking, create resources and run training at scale.
Key Responsibilities:
Own the AI R&D transformation and Agentic SDLC agenda across multiple clients: assessments, KPIs, rollout plans, training, champions programs, skills/agent developments, etc.
Lead AI Coding Tooling optimization end-to-end, plus evaluate/compare adjacent tools (e.g. Claude Code, Cursor, GitHub Copilot, Kiro, etc).
Create training materials (slides, exercises, demos) and deliver workshops; Train teams yourself and mentor trainer bench.
Develop AI infra & tooling, dashboards, frameworks, playbooks and AI resources (skills, agents, hooks, MCPs, etc) for clients to enable transformation, automation and governance
Partner with Sales/Delivery on pre-sales to attract new customers.
Stay on the cutting edge of releases and best practices, turn learnings into repeatable packages.

We are looking for an ATE Engineer to join our multidisciplinary team in central Israel.
The role involves developing and implementing complex automated test solutions, from requirements analysis through direct integration with hardware and Automated Test Equipment (ATE).
Key Responsibilities
Translate Test Requirements Documents (TRD) into automated Test Sequences/Scenarios using NI TestStand or OTM (ORION).
Develop, maintain, and enhance automated test sequences and deploy them in laboratory environments.
Integrate measurement instruments and communication protocols with ATE systems, perform debugging, and support troubleshooting activities.
Develop software components and DLLs in C# or C for hardware communication, when required.
Work closely with Hardware, Electronics, and Integration teams, including reading and interpreting electrical schematics.

We are looking for an Analytics Engineer (contract) to join Artifactory Product Analytics and build the data platform behind how we measure our products. You will own the engineering side of analytics: designing product telemetry with PMs and R&D, modeling that data into trusted, reusable datasets in the warehouse, and making those datasets easy for analysts and stakeholders to consume. Product analysts own the product questions and metric definitions; you make the data underneath them fast, consistent, and dependable.
You will work inside an AI-native analytics environment (Cursor, Claude, and similar coding agents) as the default way of shipping - not as an optional add-on.
Fixed-term contract: 6-8 months. Start date: October 12, 2026.
Responsibilities:
Design telemetry: partner with PMs and R&D to define event and data specs for product usage - schemas, properties, validation, and the path into the warehouse (core, ongoing part of the role)
Build the modeled layer: develop and maintain dbt transformation models (staging → intermediate → gold) so Artifactory product data is consistent, tested, documented, and reusable
Enable self-serve: with the analysts, design and implement how stakeholders reach certified product data so recurring questions don't need a custom pull
Align definitions: standardize entities, grain, and model structure across Artifactory areas together with the analysts who own product meaning
Ship in an AI-native workflow: specs, SQL, dbt models, reviews, and documentation done in Cursor / Claude and equivalent tools.

This role sits at the intersection of AI and high-performance systems engineering, focused on solving real-world problems under strict constraints. You will work on systems where performance and reliability are critical and where improvements have a direct, measurable impact on real-world safety.

This is a senior, systems-focused role with end-to-end ownership over performance and reliability of production computer vision pipelines. You will define optimization strategies, identify bottlenecks across the system, and drive improvements under real-world constraints.

What youll do
Build and optimize real-time computer vision pipelines running on edge systems processing live maritime video streams (e.g, NVIDIA Jetson, Triton Inference Server).
Take models from research and turn them into production-ready, reliable components deployed on vessels.
Profile and improve end-to-end system performance across: multi-camera video ingestion; preprocessing; inference; postprocessing.
Identify and resolve bottlenecks across CPU, GPU, memory, and pipeline coordination.
Make and justify tradeoffs between latency, accuracy, stability, and resource utilization.
Design and implement robust data and inference pipelines (video -> model -> actionable output for crew).
Develop benchmarking and evaluation workflows to measure performance end-to-end and support release gating.
Build and improve observability tools, including logging, monitoring, and debugging workflows for production systems.
Define and maintain clear interfaces between research code and production systems.
Work closely with research and backend teams to integrate new models into production systems.
Continuously improve system efficiency and reliability under hardware and runtime constraints.

Required RTL Design Technical Lead, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use the ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead the Design Activities at IPs, SubSystems(S.S) and SoC.
Plan, execute, track progress, assure quality, report status of the assigned activity.
Lead a team of designers both directly and in teams.
Define the Block/SoC level design documents such as Micro Architectural Specifications.
Own IP, S, SoC strategies for clocks, resets, and debugs. Enforce global methodologies and drive enhancements.

We are looking for a Senior Automation QA Engineer (AQA) to join a team delivering mission-critical systems for a leading financial institution. You will own test automation end-to-end across a layered banking architecture, building the frameworks, suites, and pipelines that keep quality high in a secure, highly regulated environment.
This is a hands-on senior role for an engineer who treats test code with the same rigor as production code. You will define automation strategy, drive coverage across UI, API, and integration layers, and embed automated quality gates into the delivery process. We build with modern, AI-assisted workflows, so QA engineers who are fluent with tools like Cursor and Claude Code will feel at home.
Architecture You Will Test
You will design and maintain automated coverage across all tiers of a layered banking architecture, validating behavior and data flow as it moves through each layer:
Client (React) → BFF (Next.js / JavaScript) → Middleware (.NET / C#) → Core Banking
Key Responsibilities
Design, build, and maintain automated test frameworks and suites across UI, API, and service/integration layers.
Automate end-to-end UI tests for the React client and BFF, and API/contract tests for the .NET middleware and core integrations.
Build, maintain, and optimize automated test pipelines in CI/CD, and embed quality gates into the build and release process.
Define test strategy, test plans, and coverage; partner with developers on where unit, integration, and end-to-end tests belong.
Validate asynchronous and event-driven flows (e.g. RabbitMQ / Kafka) and verify data integrity across services and databases.
Triage failures, perform root-cause analysis, log and track defects, and report on quality metrics and release readiness.
Work within the bank's SDLC and governance - change management, environment promotion, and compliance gates.
Mentor team members on automation best practices and raise the overall quality bar.

We are hiring a Senior Robotics Software Engineer to build the system the autonomy runs inside. You own the runtime - ROS2 architecture, module lifecycle, orchestration, state management, configuration, fault handling, and both ends of the stack: World Model ingestion and the Vehicle Interface down to the platform control systems.

You will face hard real-time constraints, embedded compute, and a system that has to keep behaving correctly when parts of it do not. You own the stack across its full depth, from the interfaces at its edges to how the whole thing behaves in the water.

What Will You Do?
Own the autonomy runtime: ROS2 and modern C++ architecture, module lifecycle, orchestration, state management, data flow, configuration, fault handling and recovery
Implement the system's two contracts: World Model ingestion and Vehicle Interface adapters to the platform control systems
Own deployment to the vessel compute: builds, packaging, versioning, configuration management and CI
Work with system engineering and field teams on vessel bring-up, sea trials and debugging in the field
Build logging, recording, replay and observability - the ability to take any run at sea and reproduce it exactly on a desk
Integrate and operate the simulation environment (SIL)
Own reliability, timing and performance of the stack on embedded hardware