לוח משרות דרושים חשמל ואלקטרוניקה

We are looking for an experienced Senior Signal Integrity Engineer to join our Hardware Engineering team. This role focuses on ensuring optimal signal integrity for high-speed interfaces, including Ethernet, PCIe, DDR5, and other next-generation technologies. As part of the team, you will be responsible for performing signal integrity analysis, developing signal integrity models, and ensuring electrical compliance for high-speed SERDES I/Os.

Responsibilities:

Conduct signal integrity analysis and simulations for high-speed interfaces such as 112Gbps Ethernet, PCIe Gen5, and DDR5 interfaces.

Develop and implement signal integrity guidelines for PCB design, ensuring high-performance and low-loss signal paths.

Analyze and resolve signal integrity issues related to high-speed interfaces, including reflection, crosstalk, and power delivery network (PDN) issues.

Collaborate with PCB layout engineers to optimize design for signal integrity, ensuring compliance with electrical standards and high-speed design best practices.

Perform time-domain and frequency-domain analysis, including loss, jitter, and eye-diagram analysis.

Utilize EDA tools such as Ansys SIWAVE, HFSS, or similar for simulation and validation of signal integrity designs.

Work closely with cross-functional teams to integrate signal integrity considerations into the overall hardware design process.

Develop behavioural models based on measured signal integrity data to inform future design and simulation work.

Conduct pre- and post-layout simulations and measurements for high-speed signal interfaces.

We are looking for an experienced Senior Power Integrity Engineer to join our Hardware Engineering team. This role will be critical in establishing power integrity guidelines, recommending supply noise design solutions, conducting IR drop and VRM performance analysis, and ensuring optimal power distribution across our high-speed platforms. As part of the team, you will also assess the effectiveness of PCB decoupling solutions and develop power integrity models.

Responsibilities:

Establish and implement power integrity guidelines for high-speed electronics.

Select & Conduct IR drop and voltage regulator module (VRM) performance analysis to ensure reliable power distribution.

Develop power integrity models based on measurement data to optimize power delivery.

Analyze and design for optimal PCB decoupling strategies to mitigate noise and ensure stable power delivery across the board.

Perform simulations and analysis on power noise, current profiles, and supply voltage integrity.

Perform power noise and jitter simulations to assess the impact of power delivery on signal integrity.

Use tools like Ansys SIWAVE, Cadence Sigrity and similar to analyze and simulate power integrity across high-speed platforms.

we are looking for a talented and experienced engineer to lead design activities and help our group drive the next era of computer architecture. In this position, you will design the critical parts of future chips. You will transform architectural requirements into micro-architectural specs, implement key blocks in RTL, and participate in post-silicon activities.
Responsibilities
Define and drive the design of advanced blocks from micro-architecture phase to netlist
Support timing and constraints definitions work closely with the BE team on timing and physical implementation efforts
Leading processes relating to power optimization
Technology expert, building a knowledge base for the group
Work with various teams to drive execution (SW, Architecture, verification, BE, etc)
Devise execution indicators and monitor and report execution progress to enable prioritization and clear decision making