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We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

We are now looking for chip-design and verification student for the Switch Silicon group.

As a chip design student in our company Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a combined design and verification team which develops some of the switch silicon core units specializing in quality of service.
Build reference models, verify and simulate chip blocks/entities according to specifications under challenging constraints with high orientation to power, area, and performance.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.

We are looking to hire a deeply technical, creative, and hands-on advanced-development researcher to prototype and evaluate novel networking technologies for our Ethernet datacenter solutions, focusing on distributed AI training, High-Performance Computing, Cloud, Storage, network programmability, end-to-end network software stacks, and SDN. We are a world leader in high-performance computing technology, AI, and networking with ambitious plans for future systems. This position offers the opportunity to have a real impact in a research-focused team in a dynamic company. The networking advanced-development group is chartered to research and incubate new technologies that will re-define the future data centers and supercomputer performance and functionality. Advanced development software researchers represent us in open-source projects, conferences, and standard bodies.

What you'll be doing:

Developing proof-of-concept implementations of new technologies, and thereafter guiding their incorporation in company products.

Evaluation and analyzing new technologies at scale.

Optimizing collective communications and distributed AI training, and HPC communications. Improving performance on our supercomputers, researching distributed solutions for next-gen data centers networking.

Software development and architecture, ranging from application behavioral analysis and algorithms, network simulations, middleware, and API design, down to implementing OS subsystems, device drivers, FW, and HW modeling.

Customer engagements, academic research collaborations, publishing white papers, blogs, RFCs, and conference lectures/BOFs.

We are looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What youll be doing:

Work in a combined design and verification team.

Design and verification for chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area, and performance.

Daily work involves all aspects of chip development: Design, Micro- Architecture, Firmware, Production, and Verification.

We are looking for a Senior Chip Design Verification Engineer for developing the next generation DFT technologies.

As a Senior Chip Design Verification Engineer in the DFT team in our coompany, you will verify the design and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our DFT solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.

What you'll be doing:
In this position, you will be responsible for verification of the DFT design, architecture and micro-architecture using sophisticated verification methodologies.
As a member of our DFT verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.
Collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

This is a highly visible position in CSG (Switching Group). We are looking for DFT engineer that wants to be part of the best implementation team, that performs a true RTL to production.
The DFT position involves ownership of testability, methodology and execution for assigned projects. The DFT engineer is responsible from RTL DFT insertion to final test program bring-up. The DFT engineers are implementing Boundary scan, MBIST, SCAN and SCAN compression, and more. They are generating all patterns and work on the chips final test programs.

Required DFT/Synthesis Design Engineer
Responsible for writing timing constraints, running synthesis and implementing DFT (including scan, MBIST and IP testing), you will work on our next generation 5G IC and interact with software, signal processing algorithms, integration and layout teams.

Required ASIC Design Engineer
Within the BBIC team, you will be responsible for the specification, design and validation of various modules linked to our next chipsets generation.
You will work closely with our other teams (software, signal processing algorithms and integration).
RESPONSIBILITIES
Micro-architecture definitions at the unit level
Specification, design, RTL coding and optimization of complex blocks
Close work with the verification team on block/top level to ensure timely delivery of quality designs.

Required ASIC Verification Engineer
Verification Group in a growing group responsible for pre-silicon ASIC Verification of complex chips implementing an advanced modem technology.
As part of the role, you will architect, develop & own blocks / sub-subsystem / system-level verification benches. You will be a major contributor to advanced SV UVM methodologies and to infrastructure development. You will be part of an advanced development flow, using state-of-the-art development & Verification tools and will work closely with the chip architects and RTL / VLSI design teams.
RESPONSIBILITIES
The Verification Engineer will be responsible for different HW blocks at module-level and sub-system level and is expected to:
Have an expert-level understanding of assigned HW blocks as well as a good understanding of the block in the context of whole system.
Communicate with architect, designer, algorithm and other verification engineers to lead complex verification tasks, both on module-level and sub-system testing.
Design complete verification environments.
Implement design in full UVM environment.
Perform full block regressions and collection of functional coverage.

Required Back End Engineer
Working with an ASIC design team, you will participate in the development of next generation SoCs for 5G and 4G wireless network.
You will be responsible for the physical implementation of the chip, from synthesis netlist to GDSII, for power and area optimized chips in advanced nodes (12 nm, 22 nm).
You will also be responsible for the physical verification of the chip.

This position will be part of the Engineering Department. We are looking for an experienced PCB designer.

Location:
Based at the RAD offices in Tel Aviv. Hybrid option twice/week.

Responsibilities:
Components library design.
PCB design, including PCB technology definition, and constraints definition. Support for PCB manufacturing and assembly.

We are looking for a C++ Team Leader.
Your Impact:
Owning features from design and development to production.
Implement cross-platform solutions while effectively utilizing the capabilities of each platform.
Perform code run time and memory footprint optimizations on various platforms.
Manage your team members and collaborate with colleagues in solving complex problems and overcoming design challenges.

We are looking for a talented C++ engineer to join our Tel Aviv R&D center.
If you want to have a key role in the development of a cross platform, High availability & high performance-oriented fintech product, Come join us.
Your Impact:
Owning features from design and development to production.
Implement cross-platform solutions while effectively utilizing the capabilities of each platform.
Perform code run time and memory footprint optimizations on various platforms.
Collaborate with team members and colleagues in solving complex problems and overcoming design challenges.