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We are seeking an experienced Software Team Leader to lead the design, implementation, and optimization of our graph compiler key backend functionalities. You will own and drive the development of compiler infrastructure that transforms high-level computational graphs into efficient, hardware-optimized execution flows. This role combines deep technical leadership with people management responsibilities.
Responsibilities:
Take full ownership of key components within the graph compiler backend. Lead, mentor, and grow a team of talented software engineers; set priorities, review designs, and ensure timely, high-quality delivery. Drive the definition and the implementation of backend compiler architecture to support various graph IR transformations, optimization passes, and hardware abstractions. Lead the identification and implementation of compiler-level optimizations to maximize performance and efficiency of workloads on target hardware. Drive clear and transparent work planning by balancing performance goals and time-to-market considerations, fostering a proactive can-do mindset across the team. Establish best practices for code quality, testing, documentation, and continuous integration within the compiler team. Work closely with frontend compiler, runtime, architecture and hardware design teams to ensure seamless integration across the software stack.

We are looking for a hands-on leader to head a small team that builds simulation models for our next-generation AI hardware and DSP. Modeling is done in several layers, from cycle-accurate, bit-exact block level modeling, to event-driven full IP system flows.
Your groups mission is to take part in the exploration phase of a project, giving architects rapid, high-fidelity feedback so they can explore design options, and to perform algorithmic regression, detecting deadlocks, sweep parameters and features, and understand system-level impact in a quickly adapting, dynamic development environment.
Beyond pure performance modeling, youll keep a sharp eye on functional accuracy and QA, follow emerging academic and industry trends, and inject the relevant insights into the product.
You will also champion modern AI-assisted coding tools (e.g., Cursor AI, GitHub Copilot) to lift the productivity of the senior software engineers on your team and shorten iteration cycles.
Responsibilities:
Lead and mentor a team of simulation and modeling engineers; set goals, review designs, and remove roadblocks. Design and implement transactional / cycle-accurate / bit-exact / event-driven models that faithfully represent advanced AI IP blocks (Transformers, CNN accelerators, custom DMA, interconnects, power-management units, etc.). Build automated flows to sweep architectural parameters and features, collect metrics, and visualize system-level impact on performance, area, power, and bandwidth. Analyze and debug complex issues such as deadlocks, race conditions, and performance hotspots; deliver concise root-cause reports and actionable recommendations. Collaborate daily with architecture, VLSI, compiler, and firmware teams to translate new algorithms and hardware ideas into model requirements and specifications. Own accuracy and QA of the simulation stack: golden-model alignment, coverage tracking, regression health, and release sign-off. Continuously survey academic papers and industry trends, extract meaningful insights, and propose innovative modeling techniques or architectural directions. Promote the adoption of AI-powered development tools to accelerate coding, code-review, documentation, and test generation across the team.

we are looking for a R&D Project Manager.
In this role, you will be managing the MBBU projects involving multiple domains including: VLSI architecture, VLSI Design, VLSI verification, VLSI backend, Algorithms and Software. These projects include development of products like cellular modems, Communication Digital Signal Processors and Radar/Lidar baseband with a total of up to 100 R&D engineers involved.
This role is reporting to the MBBU General Manager.
Responsibilities :
Full ownership on all R&D projects of the Mobile Business Unit, including Software, VLSI and Algorithms tasks.
Direct management for the PMO

we are looking for a Senior Hardware Architect for Mobile broadband.
As a senior architect you will be a leader, someone who brings into the company new ideas and helps drive next generation wireless products
Responsibilities:
Be a leader in the Mobile Broadband team, architecting state-of-the-art modems for next generation cellular solutions. Investigate, invent, develop, innovate wireless modem components. Drive the implementation phase with the VLSI, Software and Algorithm teams.

we are looking for a Senior VLSI Design Engineer.
As a Senior VLSI Designer, youll lead the full design flow of advanced DSP cores and accelerator- from architecture to timing closure. This hands-on role is key to developing the IPs behind the next-generation products, with strong cross-functional collaboration and technical ownership.
Responsibilities:
As a Senior VLSI Designer, you will be responsible for the end-to-end design and implementation of advanced digital IPs, including DSP cores and hardware accelerators. You will work across the full design flow- from architecture definition and micro-architecture design, through RTL development and verification, to synthesis, timing closure, and static timing analysis (STA). Your work will directly contribute to the silicon success of next-generation products across various domains.

We are seeking a highly skilled and motivated VLSI Backend Team Leader to join and lead our dynamic team.
As part of this position, you will lead a team of experienced engineers working on parallel projects, and play a crucial role in the design and implementation of complex designs, flow development, and the latest technology node bring-up and integration.
The Backend team leader will be required to do 50% hands on work and 50% managerial work.

We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today, such as car and Pharmaceutical. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:

Define the NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).

Research of various solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.

Developing models for simulations and performance testing, analysing the results and development of future HW and SW.

Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

Our team propels generative AI forward by building and deploying agentic systems that integrate innovative LLMs with domain tools to expedite HW and SW engineering workflows at scale. We are in search of a top-tier AI Agents Solution Architect to work closely with hardware architects, verification engineers, GPU performance experts, and software developers to develop end-to-end agent flows that drive significant enhancements in simulation analysis, kernel optimization, and developer efficiency.

What you'll be doing:

Develop innovative AI flows to improve hardware and software through collaboration with various engineering roles.

Facilitate co-creation workshops to transform SME rules of thumb into specific assignments, resources, cues, and guidelines. Define success measures, evaluation data, and feedback loops for agents to make a measurable difference in our HW simulation analysis and GPU-kernel optimization workflows.

Rapidly prototype and thoughtfully productize; integrate with internal services, utilize GPU capabilities, remove bottlenecks, and deliver fitting solutions.

Set up evaluation backbone using offline golden sets and online telemetry for confident iterations, cost control, and safe improvements.

Mentor and improve teams through insights in agent orchestration, prompting, RAG, observability, crafting documentation and playbooks for our teams.

We are looking for a passionate, modern software engineer or junior architect early in their career. The role involves developing and prototyping new scalable training and inference advancements using our Spectrum-X AI fabric.

This role offers a rare opportunity to work on innovative AI and networking technologies, building prototypes that influence the development of large-scale AI systems. You will help improve AI application-network interaction by refining communication, crafting congestion control, contributing to NIC and switch capabilities, and enhancing AI factory performance at scale.


What youll be doing:

Prototype end-to-end solutions to improve distributed training and disaggregated inference performance.

Analyze and optimize communication flows across application, transport, and network layers.

Develop system software spanning communication libraries, drivers, and firmware integrations.

Collaborate with hardware, firmware, and SDK teams to co-design network features.

Validate and integrate prototypes into our AI infrastructure and products.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:

Lead the end-to-end execution, tracking, and convergence of chip-level CDC and RDC for complex SoCs across all IPs and partitions.

Plan and orchestrate CDC/RDC signoff: define methodology, scopes, run plans, constraints, and acceptance criteria.

Run and maintain CDC/RDC flows and rule decks, including multi-mode, multi-clock, and hierarchical signoff.

Triage violations efficiently: root-cause to RTL, constraints, tool setup, or IP models; prioritize and drive fixes to closure with owners.

Verify reset architecture and RDC robustness (reset domain intent, release sequencing, glitch detection, fanout).

Author and review CDC/RDC constraints, waivers, and justifications; ensure auditability and signoff quality.

Automate runs, report parsing, dashboards, and KPIs for closure tracking using scripting and data tooling.

Partner with RTL, DV, DFT, STA, PD, and Architecture to align fixes, manage ECOs, and protect CDC/RDC quality during late design changes.

Define and enforce signoff gates; communicate progress and risks with clear metrics and issue tracking.

Continually improve methodology and training to prevent recurring CDC/RDC issues and accelerate convergence.

Our Networking BU is looking for Senior Software Program Manager that will be responsible for software programs and projects. The PM should drive planning and execution of FW/SW projects while aligning with corporate priorities and constraints.

Our Mellanox Networking division is a leading supplier of innovative end-to-end InfiniBand and Ethernet connectivity solutions and services for servers and storage. We offer best-in-class solutions that include adapter cards, switches, cables, and software to support networking technologies. Our products optimize data center performance and deliver industry-leading bandwidth and scalability. In addition, we serve a wide range of markets including high-performance computing, enterprise, data centers, cloud computing, big data and Web 2.0. We are constantly reinventing ourselves to stay ahead of the market and bring groundbreaking products and services to the industry. Our product line is focusing on delivering the most optimized Ethernet solutions for industries like Media and Entertainment as well as any other industry that can benefit from our Datastream and TCP/IP acceleration.

What you'll be doing:
You will manage the networking software programs for our next generation AI Data centers.
Responsible to coordinate between all project stakeholders such as marketing, engineering teams in IL and around the world, operations, etc. from initial requirements definition through Architectural stage, execution, and delivery.
Develop and execute feature planning and prioritization of perception capabilities to meet the software programs' needs.
Identify risks, gaps, and bottlenecks in time, and find resolution with technical leaders and project management.
Work with product managers, architects, and engineers to ensure consistency with company strategy, commitments, and goals.

As a Senior Software Architect in the GPU Networking Architecture team, you will define Software Defined Networking architectural solutions. You'll also be part of a team of specialists who span across numerous technological fields related to the modern data center, such as distributed AI and deep learning systems, Networking Operating Systems, Virtualization, Storage, and more.

What youll be doing:
Define system and software architecture for Software Defined Networking (SDN) of ground breaking emerging AI networks which involves innovative software and hardware.
Be an active member in setting the use-cases and metrics for Monitoring Complex High-speed Networks Control-plane.
Work closely with various groups within us to bring AI network technologies to reality, including GPU and Switch HW and SW teams, Product as well as fellow architects.

As a Senior Software Engineer in the GPU Networking Architecture team, youll lead advanced development and POC efforts for AI infrastructure solutions. You'll be collaborating with experts across distributed AI, deep learning, networking OS, virtualization, storage, and more. Come and join us for the cutting edge in GPU Networking!

What youll be doing:
Drive advanced development and POCs for AI infrastructure solutions in cutting-edge AI networks, integrating innovative software and hardware.
Demonstrate team architectural concepts with larger NVIDIA AI software stacks.
Work closely with various groups within NVIDIA to bring AI network technologies to reality, including GPU and Switch HW and SW teams, Product as well as fellow architects.

As a Senior Software Architect in the Accelerated Computing System and Software team, you will define Software Defined Networking (SDN) architectural solutions and be part of a team of specialists who span across numerous technological fields related to the modern data center, such as distributed AI and deep learning systems, High Performance Computing (HPC), Networking Operating Systems, Virtualization, Storage, and more.

What youll be doing:

Define system and software architecture for Software Defined Networking (SDN) of ground breaking emerging AI and HPC networks which involves innovative software and hardware.

Be an active member in setting the use-cases and metrics for Monitoring Complex High-speed Networks Control-plane.

Work closely with various groups within NVIDIA to bring AI and HPC network technologies to reality, including GPU and Switch HW and SW teams, Product as well as fellow architects.

We seek a highly motivated and experienced Software Architect specializing in Ethernet Switch ASICs to join our team of experts and help shape the future of high-performance ML/AI computing. You will have the opportunity to work on some of the most pioneering technologies and help drive the innovation of our next-generation networks. You will play a key role in defining switching software stacks and Linux kernel networking, and help address new business opportunities in exciting areas. Our Architects also represent us in open-source projects, technical conferences, and standard development organizations.

What you'll be doing:

Explore networking technologies, features and protocols, hardware/software capabilities, open-source software and drivers for our Ethernet Switch ASICs and Networking platforms.

Be familiar with the Ethernet Switch ASIC hardware and software stacks, as well as with the Ethernet Switch platforms design and characteristics.

Define robust architectures and technical requirements for embedded software, meeting AI/ML workloads' needs and highly performing network operations.

Lead the work with R&D and Validation teams, providing technical guidelines and close support and thorough reviews for detailed designs and test plans.

Collaboration with architects across various fields, including Chip Design, Firmware, Hardware Platforms, and System teams.

Close work with product marketing, program managers, and account managers to ensure the successful execution of projects.

Support engagements with key customers, issue patents, publish white papers and blogs, and be proactive in technical forums and industry working groups.

Promote innovation through the design and implementation of Proof-of-Concept (PoC).