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As a Machine Learning Software Engineer, you will join our AI Engineering group of our company:
Our goal is to deliver a modern infrastructure and solutions to enhance our company's algorithm development life cycle and shorten our delivery times.
We are an independent group, consisting of excellent and experienced engineers with diverse skills in software, infrastructure and algorithms.
We strive to implement a DevOps culture allowing our engineers to easily collaborate on large-scale products. We develop products that enable the research and deployment of state-of-the-art algorithms.
It develops the tools and sets the standards that allow great research.
What will your job look like:
Work closely with algorithm developers and infrastructure engineers to design, develop and automate the software that supports distributed training of deep learning algorithms.
Set the standard for developing reliable software, allowing reproducible research at scale.
Build and improve data pipelines to make the development process for deep learning algorithms more efficient.
Develop products that help algorithm developers test their models on large-scale real-world data. Our tech stack includes: Pandas, Polars, PyTorch, Kubernetes, Argo-Workflows, Spark, AWS.

The company's EyeC VLSI team specializes in designing advanced radar system chips for ADAS (Advanced Driver Assistance Systems) and autonomous vehicles. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
Design ownership on major blocks/clusters from definition to implementation phase.
Participate in various ASIC activities and flow definition which includes CDC, DFT, Lint.
Design micro-architecture of custom blocks.

our company's EyeC VLSI team - a group designing the chips for RADAR systems for ADAS and autonomous cars.
Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges
Were looking for a Experienced Physical Design Engineer to join the growing Physical Design Team, responsible for developing our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS with horizontal ownership.
Floorplan exploration and collaboration with front-end and architecture teams.
Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification.
Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA.
STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff.

The company's EyeC VLSI team designs chips for RADAR systems used in ADAS and autonomous vehicles. Our Physical Design team operates in a startup-like environment, emphasizing technical expertise, execution, and ownership. Each engineer in the Physical Design team takes full responsibility for their work, from initial definition through execution and final sign-offs. Engineers collaborate closely with design and architecture teams to develop constraints, conduct design reviews, and implement RTL modifications to ensure convergence.
We are seeking an Experienced Backend to join our growing Physical Design team. In this role, you will play a key part in the design of state-of-the-art SoCs, from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

Each of our Experienced Python Developers codes and enhances our products and frameworks, shaping the way of work for hundreds developers in our company. We focus on technology, reliability, and usabilityall this at exceptionally large scales of computing, storage, codebase, data, and more.
We are looking for a talented Python Developer to join us in scaling up our infrastructure and services, working across multiple teams in areas related to development, automation, algorithms and CI.
What will your job look like:
Collaborate with different algorithmic groups in our company
Work with highly experienced developers and architects.
Work on a large-scale system from its early stages and watch it evolve
Take part in the design & development of a multi-service cloud-based big data platform
Deliver a high-quality product, which is a standalone tool, fully developed in our team.
See your tools being used by hundreds of users, where every improvement, optimization, and a new feature is based on real requirements and is usually very significant to their daily work.

our company EyeC VLSI team - a group designing the chips for RADAR systems for ADAS and autonomous cars.
Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges
Were looking for a Experienced Physical Design Engineer to join the growing Physical Design Team, responsible for developing our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS with horizontal ownership.
Floorplan exploration and collaboration with front-end and architecture teams.
Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification.
Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA.
STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff.