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We're looking for Electrical Engineering graduates to join the Pre-Silicon Verification Team based in Haifa.

As a Junior Pre-Silicon Verification Engineer, you'll work at the heart of chip development, collaborating across teams to ensure our semiconductor platforms meet the highest standards before they reach production.
IO verification team will expose you to the most advanced technologies , as we lead the market with our leaving devices - youll soon have to expertise most advance protocols

A day in the life
In this role, you'll engage in pre-silicon verification work that connects every phase of our product development journey- from initial product definition through firmware and software development.
You'll collaborate with hardware designers, software engineers, and cross-functional teams to validate complex semiconductor architectures and protocols.
Your days might include developing and executing verification test plans, analyzing simulation results, troubleshooting design issues, and participating in design reviews.
You'll work with advanced verification methodologies and tools, gaining exposure to cutting-edge technologies that define the next generation of cloud infrastructure.

We are looking for an experienced Senior DevOps & Platform Engineer to join our DevOps team and help customers modernize their software delivery platforms, cloud infrastructure, and engineering practices.
This role combines hands-on engineering, software development, platform architecture, and customer-facing consulting. You will work directly with customers to assess their development lifecycle, understand their tooling and processes, and design scalable, secure, and automated solutions that accelerate software delivery and improve developer experience.
Responsibilities:
Design, implement, and maintain cloud-native platforms across AWS, Azure, and Kubernetes environments
Implement and optimize Kubernetes platforms and cloud infrastructure solutions for enterprise customers
Build CI/CD pipelines, GitOps workflows, Infrastructure as Code solutions, and deployment automation
Develop automation, integrations, and platform services using Python, Go, and modern engineering practices
Lead customer discovery sessions, technical assessments, and workshops to understand existing development and operational processes
Interview Development, Operations, Security, and Leadership teams to identify challenges and improvement opportunities
Design target-state architectures, platform roadmaps, and implementation plans
Implement observability, monitoring, logging, and security best practices across customer environments
Deliver technical presentations, workshops, and knowledge-transfer sessions
Contribute reusable automation, documentation, and internal platform assets

We're looking for exceptional engineers to join our Signal/Power-Integrity and Packaging team. A team that sits where the Silicon meets the Board, bridging the gap between what happens internally at the DIE and the overall system interconnect and the external memories and peer devices.
What sets us apart:
Small team, yet a one stop shop for IP electrical integration at the DIE level, Package design, SI/PI simulations, Layout, Board-design and advanced lab characterization.
Combining Signal-Integrity and Layout, to come up with optimized Package and PCB designs.
Holistic view of the entire interconnect, from the DIEs metals, through the Package, to the PCB traces, and all the way to the peer device.
In-depth post-silicon characterization, using advanced measurement techniques, far exceeding traditional compliance measurements.
Deep dive mentality, in both theory and the bolts and nuts that make the internal circuitry of the electrical interfaces.

The SIP (Signal-Integrity & Packaging) team is part of Annapurna-Labs Chip development team.
The team is dealing with the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
The teams work includes close work with the BackEnd team on integrating these interfaces to the Die, the package layout design of the BGAs substrate, Signal and power integrity simulations, and working with the system team to come up with optimal pin-out and optimal PCB breakout schemes.
We are looking for highly motivated Electrical Engineering graduates, or engineers with up to 3 years' experience in related fields, to join our growing team specializing in Signal Integrity and IC Package Design. The position offers a unique entry point into a diverse and multidisciplinary domain.

Key job responsibilities
Work on advanced high-speed interfaces such as PCIe, DDR and Ethernet.
End-to-end solution of high-speed interfaces; from floor-planning at the DIE level, through Package and PCB routing, addressing both robust SI/PI considerations as well as optimizing layout routing.
Signal and power integrity modeling and simulation of high-speed interconnects using advanced SI/PI simulation tools.

We're hiring a hands-on delivery engineer to take Cortex deployments from initial setup through production rollout and keep them running well afterward. You'll own the technical execution of Cortex projects for our customers: standing up the platform, onboarding data sources and endpoints, tuning detections, and building automation playbooks. Once a deployment goes live, you'll also pick up operational issues for it and for other customers.
Responsibilities:
Configure and deploy Cortex XDR, XSIAM, and XSOAR, translating architecture and design decisions into a working environment
Lead endpoint agent rollout, log source and data onboarding, and integration configuration across a customer's security and IT stack
Tune detection rules and correlation logic to reduce noise and align with each customer's environment and threat profile
Build and maintain XSOAR playbooks that automate response actions and reduce manual triage work
Troubleshoot production issues across the platform: agent health, ingestion failures, integration breakage, playbook errors, and detection gaps
Write clear documentation and runbooks
Escalate to Palo Alto support channels when an issue requires vendor involvement, and manage the case through to resolution
Validate a project's technical scope against the signed SOW before kickoff, and flag gaps or risks early

We're looking for exceptional engineers to join our Signal/Power-Integrity and Packaging team. A team that sits where the Silicon meets the Board, bridging the gap between what happens internally at the DIE and the overall system interconnect and the external memories and peer devices.
What sets us apart:
Small team, yet a one stop shop for IP electrical integration at the DIE level, Package design, SI/PI simulations, Layout, Board-design and advanced lab characterization.
Combining Signal-Integrity and Layout, to come up with optimized Package and PCB designs.
Holistic view of the entire interconnect, from the DIEs metals, through the Package, to the PCB traces, and all the way to the peer device.
In-depth post-silicon characterization, using advanced measurement techniques, far exceeding traditional compliance measurements.
Deep dive mentality, in both theory and the bolts and nuts that make the internal circuitry of the electrical interfaces.

The SIP (Signal-Integrity & Packaging) team is part of Annapurna-Labs Chip development team.
The team is dealing with the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
The teams work includes close work with the BackEnd team on integrating these interfaces to the Die, the package layout design of the BGAs substrate, Signal and power integrity simulations, and working with the system team to come up with optimal pin-out and optimal PCB breakout schemes.

As a SIP team member, you will assume responsibility for all electrical aspects of physical interfaces of advanced I/Os, PLL, Memory and SerDes interfaces, from integration at the Die level, through SI/PI simulation and package layout, to reference board design aspects.

This position is for an experienced engineer with strong background in high-speed electrical interfaces, such as DRAM, PCIe, Ethernet SerDeses. The line of work is multi-disciplinary, combining Package-Design, Back-End integration of electrical IPs, SI/PI extractions & simulations.


Key job responsibilities
Deep dive into electrical IPs, integrated into the DIE;
I/O ring design and close work with Backend team on floor-planning all I/O interfaces at the DIE level.
Lead test studies of Die bump-out arrangements and Package substrate breakout.
Lead layout test studies of package pin-out arrangements and PCB board breakout.
Design large and complex package substrates.
Carry advanced SI/PI extractions and simulations to validate the design from the silicon to the peer device at the board level.

We are looking for an energetic, detail-oriented individual to join our Data Center Engineering Operations Team. This committed group works to maintain the critical physical infrastructure that supports Amazon Web Services. Specifically, this team works to ensure that the data center's MEP operates at 100% availability while maintaining first-class customer service to the teams and groups within the data centers.
The Data Center Engineering Operations Facility Engineer is responsible for operating and maintaining all electrical, mechanical, and fire/life safety equipment within the data center. This person serves as a technical resource to support Amazon within its owned and operated data centers. Data center equipment that supports mission-critical servers must maintain better than 99.999% uptime. DCEO Facility Engineers are also tasked with driving innovation while reducing operational costs in the facilities.

DCEO Facility Engineers are Amazons front line responders for hands-on electrical and mechanical equipment troubleshooting and operation. This equipment includes, but is not limited to, stand-by diesel generators, switchgear, UPSs, PDUs, AHUs, chillers, cooling towers, chemical treatment systems, pumps, motors, VFDs, and building automation systems.


Key job responsibilities
- Operate and maintain mechanical and electrical equipment.
- Perform root cause analysis of equipment failures.
- Troubleshooting of facility and rack-level events within internal SLA.
- Ensure all safety procedures are adhered to while performing work.
- Able to work shifts (rotating work days during the weeks).
- Take daily operational readings of all mechanical and electrical equipment.
- Utilize internal CMMS to manage building workflows.

We are developing leading edge products, manufactured on leading edge technologies. We offer a dynamic, open, teamwork environment operating at high pace mode.

Key job responsibilities
Primary responsibilities:
- Development of DfX (DfM, DfT, DfQ&R, etc.) methodologies and BKMs (Best Known Methods).
- DfX activities during the product design stage.
- Product quality & reliability validation (QRV) and ongoing quality & reliability monitoring (OQRM).
- Q&R engineering of volume manufacturing: auditing, monitoring, risk assessment and disposition of non-conformance events/non-conforming material, defining and implementing corrective actions.
- RMAs: investigation, disposition, reporting and follow-up.

We are developing leading edge products, manufactured on leading edge technologies.
We offer a dynamic, open, teamwork environment operating at high pace mode.

Key job responsibilities
Assume full ownership of mechanical and thermal design of Annapurna ICs.
Engage with product architect and design teams on future products package and assembly needs
Perform package level thermal simulations.
Perform package level mechanical simulations.
Lead and design thermal and mechanical measurements of ICs.
Explore and provide recommendations on both available and future packaging and assembly technologies for Annapurnas products.
Engage with substrate and assembly vendors on future technologies roadmap.
In collaboration with HW Dev team optimize mechanical vs. thermal tradeoffs.
Ensure testability of the ICs in collaboration with Test Engineer team.

We are looking for an Embedded Software Engineer to join the SW group and take a major part in redefining the future of AWS cloud.

Were searching for engineers with a passion for networking to develop SRD (Scalable Reliable Datagram). SRD is a high-performance, low-latency transport protocol used within our Web Services infrastructure to optimize network performance. SRD powers several high-impact, cutting-edge products, including on-demand ML and HPC platforms leveraging EFA, next-generation storage services built on EBS, and the future of AWS network traffic.

Key job responsibilities
As an Embedded Software Engineer on the SRD team, your primary responsibility will be to develop and optimize SRD technology across AWSs network infrastructure. You will work on cutting-edge, high-performance platforms that power ML, HPC, and storage-intensive workloads.

Your role will involve designing, deploying, and maintaining the SRD codebase, ensuring its reliability and scalability to meet the demands of diverse applications. You will gain in-depth knowledge of the various platforms and services running SRD within AWS, diving deep to understand their unique challenges and complexities.

Collaboration will be key, as you will work across multiple teams at different layers of the software stack. You will also contribute to defining new hardware modules and enabling offloads to enhance performance.

As a Software Development Engineer in Test on our team, you will own the quality of Nitro card embedded software and firmware. You will design, develop, and maintain test automation for embedded systems and components, covering hardware interface verification, real-time firmware behavior validation, firmware update integrity, and fleet-scale deployment confidence. You will collaborate closely with firmware development teams to troubleshoot complex system-level problems at the hardware-software boundary and ensure timely delivery of high-quality Nitro card software to AWS Cloud solutions.

Key job responsibilities
- Own the firmware test automation framework - architect, develop, and extend a Python-based validation solution that scales across multiple Nitro card generations and hardware platforms, automating test coverage across the full firmware stack from boot sequences through board management layers and card-level system integration.
- Design and implement traceable, specification-driven test cases that validate firmware functional correctness, fault tolerance, and performance across hardware components, communication interfaces, and cross-subsystem interactions.
- Optimize CI/CD pipelines by integrating pre-merge and post-merge firmware validation, defining trigger policies per hardware generation, enforcing coding-standard compliance, and reducing commit-to-validated cycle time.
- Troubleshoot complex embedded system failures by analyzing firmware logs, system traces, and hardware diagnostics, then translate field incidents into targeted regression suites that prevent recurrence.
- Collaborate with firmware and hardware teams during new-generation silicon bring-up, define test plans, drive quality gates for production release, and mentor teammates on testing best practices and system architecture.

A day in the life
You start your morning reviewing overnight CI results and triaging any firmware validation failures flagged across active Nitro card generations. Mid-morning, you pair with a firmware engineer to debug a boot-sequence regression discovered during pre-merge testing, using hardware-in-the-loop test benches and system traces. After lunch, you join a design review for a next-generation Nitro card, providing input on testability and proposing validation strategies for new subsystem interfaces. Later, you refine your test framework to improve coverage for a recently released feature, then wrap up by sharing your findings in a team knowledge-sharing session.

Palo Alto Networks is looking for a Senior Software Engineer to join our team responsible for the machine identity and access offering, designing and developing services used as part of Palo Alto Networks' SaaS products.
The team designs and develops services that integrate closely with leading cloud vendors like AWS, Azure, GCP, and many other DevOps services and tools, providing managed access to sensitive assets in the organization.
In this role, you will be using advanced AWS micro-services, with Ruby, Golang, Java and Python through the entire SDLC from planning to production.
The team collaborates with security architects, product managers, and other development teams.
Together we produce complex and advanced solutions that meet the highest security and scalability standards.
We are looking for someone energetic and versatile to join our family and help us achieve our goals.
Design and develop new features using container-based architectures
Research new technologies and platforms
Be a member of a highly talented cross-functional development team of developers, architects, and QA engineers, in an agile oriented environment
Participate in continuous and iterative engineering cycles, emphasizing code quality, supportability, scalability, and performance.

We are seeking an experienced, people oriented Engineering Manager to lead our high-performing Identity Authentication engineering team. Driving the modernization of core, mission-critical authentication domains across our primary product, delivering massive impact at scale. In this role, you will balance technical leadership, people development, and operational execution to deliver secure, scalable, and resilient SaaS cloud services. Working in close partnership with Product Management, Security Architects, and cross-functional engineering leaders, you will foster a culture of continuous delivery, technical excellence, and innovation. You will empower a team of talented engineers, remove roadblocks, and ensure our systems satisfy demanding global scale, high throughput, and Non-Functional Requirements (NFRs).
Your Impact:
Drive agile engineering practices to deliver high-quality, production-ready features on schedule while maintaining a strong balance between feature delivery, platform health, and technical debt.
Partner with domain experts to guide architectural decisions, review designs, leveraging no-code, low-code, and AI-based solutions.
Maintain high standards for service reliability, production health, automated testing (CI/CD), and incident response.
Mentor, coach, and grow a high-performing team of software engineers; conduct 1:1s, support career development, and foster an inclusive, high-trust engineering culture.
Align team goals with Product Managers, Security Architects, and global stakeholders to translate business strategy into clear technical execution plans.

we are looking for a FX Operations Lead.
The FX Operations lead is responsible for ensuring the accuracy and reliability of FX rates displayed to customers across payment and conversion flows.
The role focuses on monitoring FX rates from external providers, validating operational controls, investigating discrepancies, and ensuring alignment with the rates received from banking and liquidity partners.
This position works closely with Product, R&D, Treasury, Finance, and Operations teams to support stable and efficient FX operations.
Hybrid
Full-time
What you'll do:
Monitor and validate FX rates across customer-facing payment and conversion flows.
Perform daily operational controls and checks for live and end-of-day FX rates.
Investigate and resolve FX discrepancies, operational issues, and payment-related incidents.
Support monitoring of FX configurations, thresholds, and provider integrations.
Work closely with internal stakeholders including Product, Treasury, Finance, R&D, and Operations teams.
Support process improvements and operational efficiency initiatives.
Maintain accurate operational documentation and escalation processes.