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The Head of C2 (Command & Control) Development will lead the design, development, and delivery of advanced control, monitoring, and decisionsupport capabilities for a nextgeneration defense system. This role requires a strong technical foundation in C2 architectures, realtime systems, and multisensor integration, combined with proven leadership experience in growing and guiding highperforming engineering teams.
Why Join us?:
This is a unique opportunity to be at the heart of a defense-tech startup during its most exciting growth phase.
Responsibilities:
* Lead a multidisciplinary development team with the ability to scale into a full C2 group as the program expands.
* Define the technical vision, architecture, and roadmap for our C2 subsystem, ensuring alignment with systemlevel requirements and operational needs.
* Drive endtoend development of control and monitoring capabilities, including situational awareness, mission management, data fusion, and operatorsystem interfaces.
* Collaborate closely with system engineering, algorithm teams, hardware teams, and operational experts to deliver robust, missionready solutions.
* Establish development methodologies, coding standards, integration processes, and Quality Assurance practices suitable for defensegrade systems.
* Mentor engineers, build team capabilities, and recruit additional talent as the group grows.
* Manage schedules, risks, and deliverables in a dynamic, multistakeholder environment.
* Interface with customers, partners, and defense organizations to understand operational constraints and ensure compliance with defense standards and regulations.

Design high-performance analog and RF ICs optimized for precision, power, and area, driving prototype and product iterations from architecture to silicon validation.

Responsibilities
Design and simulate analog and RF integrated circuits, including critical blocks such as amplifiers, mixers, PLLs, ADCs, DACs, and bias/reference circuits, with a focus on signal integrity, linearity, and precision.

Optimize circuits for power, area, and performance trade-offs, ensuring designs meet system-level requirements across process, voltage, and temperature (PVT) variations.

Collaborate closely with optics, simulation and PCB teams to define architecture and block-level specifications for successive prototypes and product iterations, ensuring tight alignment with overall performance and integration goals.

Work with layout engineers to guide floor-planning and physical design, minimizing parasitic effects and preserving analog precision in layout-sensitive blocks.

Support post-silicon validation and bring-up, defining test plans, analyzing lab measurements, and correlating results with simulation to refine future design iterations.

Language: English at a proficient level. French is a plus.

As a Digital Backend Design Engineer, you will be responsible for the physical implementation of digital designs from RTL to GDSII, leveraging cutting-edge EDA tools and methodologies. You will collaborate closely with RTL design, DFT, and packaging teams to achieve optimal performance, power, and area (PPA), while meeting stringent timing and yield targets.

Responsibilities
Execute full-chip and block-level physical design tasks including floorplanning, placement, clock tree synthesis, routing, and physical verification.

Develop and optimize the digital backend flow.

Drive timing closure, power optimization, and physical verification (LVS/DRC/ERC).

Collaborate with front-end designers to address timing and logical/physical interface issues.

Support tapeout preparation and final signoff processes.

We are seeking a data Systems Analyst We are looking for a skilled data Systems Analyst to provide data and AI-based solutions, analyze business needs, translate them into technology solutions, and support the development and implementation of data -driven systems. This role requires experience in data project analysis, Agile methodologies, complex databases, financial organizations, banking processes, data architecture, API specifications, ML models, AI solutions, and system integrations. A full-time hybrid position based in Central Israel, with 1 day a week remote. Key Responsibilities:
* Analyze business needs and translate them into data -based technological solutions.
* Define business and technological requirements with business stakeholders and development units.
* Write functional and technical specification documents, including ERD specifications.
* Support and accompany development processes.
* Work with data development teams, analysts, and data Engineers.
* Support the development and implementation of data solutions, ML models, AI solutions, and integrations with organizational systems.

Play a critical role in ensuring the functional integrity, performance, and reliability of next-generation optical chips.

Responsibilities
Develop robust verification plans for complex digital and mixed-signal optical chip designs.

Collaborate closely with architects, designers, and customers to understand logic requirements, translate them into verification strategies, and deliver clear, actionable feedback throughout the development process.

Perform netlist-level simulations with SDF back-annotation for timing-accurate verification

Support FPGA/ASIC bring-up and post-silicon validation as needed

Develop, maintain, and optimize testbenches and verification components using advanced SystemVerilog features, such as constrained random testing, assertions, and transaction-level modeling, to create robust coverage-driven environments.

Design scalable, reusable UVM-based environments and components (e.g., agents, monitors, scoreboards) for block- and system-level verification. Employ UVM to achieve regression automation, functional coverage closure, and high bug-detection efficiency.

Develop and execute verification strategies for digital blocks implementing or interfacing with PCI Express (PCIe). Apply protocol-checking, compliance validation, error injection, and debug skills for PCIe endpoints and root complex devices. Use protocol analyzers and simulation environments to validate correct implementation across all protocol layers.

Participate in the verification of RISC-V CPU cores and subsystems. Create test plans targeting processor modules (ALU, decoder, register file, control logic), with reference model comparisons, signature checks, and coverage of edge-case scenarios. Leverage formal verification and compliance suites for thorough design validation.

Plan and perform end-to-end ASIC verification, from block-level testbenches to full-chip integration. Execute functional and regression tests, formal verification, and coverage analysis. Debug and resolve design issues, ensuring pre-silicon reliability before manufacturing. Engage in design reviews and system-level protocol validation with cross-functional teams.

Design and verify custom digital hardware components and architectures that enable high-performance, tightly integrated computation workloads and interface custom tensor unit for advanced AI/ML applications.

Responsibilities
Design, implement, and verify RTL blocks for memory, control, and compute subsystems within custom multiphysics computation unit.

Collaborate with system software and architecture teams to define block-level specifications and ensure alignment with performance and integration goals.

Develop and maintain functional verification infrastructure to validate design correctness across simulation and hardware testbenches.

Support synthesis, timing analysis, and backend integration, working closely with physical design and CAD engineers.

Contribute to architectural exploration and hardware-software co-design efforts to shape future iterations of compute platform.

As a Performance Software Engineer, you will be instrumental in building the core computation software that runs on custom AI accelerators. Your work will bridge the gap between host systems and proprietary hardware, encompassing everything from a custom on-board kernels to the sophisticated tooling required for real-time debugging. You will be a key player in chip bring-up and the long-term development of high-performance computation primitives and kernels, ensuring our architecture operates with maximum efficiency and deterministic performance.

Responsibilities
Develop and optimize low-level software primitives in C/C++, assembly, and architecture-specific intrinsics, primarily for RISC-V and ARM platforms.

Implement performance-critical kernels, runtime components, hardware abstraction layers, drivers, and firmware operating in bare-metal or highly constrained environments.

Work closely with hardware architects and RTL/design teams to define and validate hardware-software interfaces, memory maps, register interfaces, interrupts, synchronization mechanisms, and boot flows.

Analyze and optimize software for latency, throughput, memory footprint, instruction count, and efficient use of processor and accelerator features.

Bring up and debug software on simulation, emulation, FPGA, and silicon platforms, including low-level hardware/software integration issues.

Develop validation tests, benchmarks, and diagnostic tools for new processor, DSP, accelerator, and SoC functionality.

Contribute to architecture decisions around ISA extensions, compiler intrinsics, memory hierarchy, DMA, cache/coherency behavior, and software-visible hardware features.