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Our Network Architecture, Modeling and Performance Insights group is seeking a skilled and driven hands-on Network Modeling Architect to conduct advanced network research and optimization while utilizing and enhancing our advanced simulation tools.

In this role, you will be a key contributor to defining the architecture and improving network performance for AI and High Performance Computing (HPC) workloads. You will be responsible for modeling advanced network topologies, configurations, logic and traffic patterns, and analyzing their effect on end-to-end performance. You will develop expertise in our simulation tools and write code daily to contribute directly to their development road map and prioritization, develop core features in the simulator, and expose the capabilities to additional users. You will take part in complex architecture decisions, define and verify the modeling assumptions, and put them to the test vs. real HW and SW performance. If you're passionate about tackling intricate challenges and contributing to comprehensive systems and working on innovative solutions, we want to hear from you.

 

What you'll be doing:

Analyze and model our AI and High Performance Computing offerings, deep dive into network behavior for training and inference and generate insights to directly impact the architecture of next-generation of AI systems. Conduct advanced network modeling, research and optimization using innovative simulation tools.

Write production-quality C++ and Python code daily. Hands-on modeling of advanced network topologies, configurations and traffic patterns representing real life AI workloads, and analyze their effect on the system's performance. Actively develop the simulator software solution while contributing modular and scalable code.

Actively support the HW and SW development life cycles, map existing and candidate features into the simulation domain to enable their analysis, impact assessment and optimization.

Take full independent ownership of the performance modeling roadmap for a defined set of features. Interface directly with internal clients, communicate the analysis conclusions effectively and iterate on them. Drive projects from concept to completion.

Improve the quality of the simulation as a software product, ensuring robustness and reliability.

We are looking for a Full-Chip verification & Integration Engineer to join our FullChip Switch Silicon team. As part of NVIDIAs Networking business unit, you will work alongside passionate and highly skilled engineers building the next generation of state-of-the-art switch silicon chips. This is a unique opportunity to grow in a technically rich environment and gain broad system-level exposure, and contribute to cutting-edge devices that deliver world-class bandwidth, throughput, and latency.

In this role, you will help integrate and validate complex full-chip flows at the system level, working across multiple engineering domains and learning how advanced silicon products come together from architecture to execution.

What you'll be doing:

Work in a Full Chip verification team that is responsible to integrate and verify our Switch products at system level.

Work closely with multiple teams within the organizations such as Architecture, u-arch, Firmware and all switch units and Ips.

Play a key role in validating the most complex end-to-end chip flows, gaining hands-on experience with system behavior, cross-block interactions, and real product-level scenarios.

Use modern AI-powered engineering tools and automation techniques as part of your day-to-day development and debug workflow.

Learn from experienced engineers in a collaborative environment that encourages technical growth, ownership, and continuous improvement.

We seek for team lead to join our Ethernet Switch SONiC Network OS. As a SONiC design team lead, you will have to work closely with our development and architecture teams responsible for SONiC Network OS and gain a deep understanding of our products and technologies.

What you'll be doing:

Be part of our SONiC R&D team, contribute code to SONiC worldwide community.

Work in a Continuous Deployment environment of fast development/deployment cycles.

Work with experienced teams which are well known in the SONiC community.

Participate in an international team of software engineers working on products for testing our products.

Manage, mentor, and guide a team of SONiC eth switch NOS.

Design and implement SONiC feature under linux environment upstream to SONiC open source project.

Promote a culture of innovation, quality, and accountability. Bring SONiC NOS to shine in customer's view.

Required AI Engineer & Architect
The Role:
As AI Architect in the ACoE, you are the technical backbone of our internal agentic transformation. You will design and build the reference architectures, standards, and shared infrastructure that enable hundreds of AI agents to run reliably, safely, and at scale - across R&D, Sales, Customer Revenue, HR, Finance, and Marketing.
This is a hands-on, highly visible role. You will split your time between deep technical work (designing agent orchestration patterns, building cross-company automations, evaluating platforms) and enabling others (code reviews, technical mentorship of citizen developers, setting standards). You will report directly to the ACoE Lead and work closely with the CTO, BI, and Platform teams.
Key Responsibilities
Architecture & Standards:
Define and maintain our reference architectures for agent orchestration, tool permissions, memory models, inter-agent communication, and data boundaries
Establish technical standards for agentic development - prompt engineering patterns, evaluation harnesses, testing frameworks, and shared agent templates
Drive tooling standardization across in partnership with the CTO and CFO, and lead the annual vendor/platform review
Build & Enable:
Develop and maintain selected cross-company agentic solutions and automation workflows
Build and maintain the shared infrastructure: monitoring integrations, KPI dashboards, the agent registry, and the ACoE knowledge base
Conduct technical reviews and code reviews for agents before production deployment
Serve as technical SME for citizen developers across all business units - unblocking, guiding, and reviewing their work
Governance Support:
Define and implement the pre-deployment evaluation harness and model card standards
Support the AI Governance Officer (initially the ACoE Lead) with technical input on risk classification, incident response, and rollback planning
Contribute to quarterly ethics audits for high-risk agents
Innovation:
Track the rapidly evolving agentic AI ecosystem and bring relevant insights and tools back
Co-author external technical content (whitepapers, conference presentations) to establish our technical thought leadership.

The CPU team is a world-class, global organization united by a mission to push the boundaries of whats possible and shape the future of computing. We are looking for a talented, fast-learning and highly motivated Logic Design Engineer to join our team. As part of the core design team, youll take ownership of parts of the design and work closely with architecture, verification, and physical design teams, contributing to a fast-moving, technology-focused environment and helping shape future products.

What you'll be doing:

As part of the CPU core team, youll take ownership of a unit.

Contributing to the micro-architecture, writing RTL and documentation.

Working closely with verification and implementation teams to meet timing, area, performance, and power goals.

We are a global pioneer of RADAR systems for active military protection, counter-drone applications, critical infrastructure protection, and border surveillance. We are looking for ATE software engineer As a Software Automatic TEST Equipment Engineer, you will play a vital role in developing and maintaining advanced Automatic TEST Equipment (ATE) software for electronic cards and calibration systems used in our cutting-edge Active Electronically Scanned Array (AESA) radar technology. You will collaborate closely with a multidisciplinary team to ensure the functionality, accuracy, and performance of our ATE systems. Key Responsibilities:
* ATE Software Development: Design, develop, TEST, and maintain software for Automatic TEST Equipment used in electronic card testing and AESA radar calibration.
* Integration: Collaborate with hardware engineers to integrate ATE software with testing equipment and devices, ensuring seamless operation.
* Debugging and Troubleshooting: Identify and resolve software issues, system failures, and compatibility problems to ensure optimal ATE performance.
* Documentation: Maintain accurate and up-to-date documentation.
*  Quality Assurance : Implement quality control measures to ensure that ATE software meets industry standards and complies with project requirements.
* Team Collaboration: Work closely with cross-functional teams, including hardware engineers, software developers, and project managers, to meet project milestones and objectives.
* Continuous Improvement: Stay up-to-date with industry trends and emerging technologies, and contribute to the ongoing improvement of ATE software and testing methodologies.

We are seeking for an Project Planning Engineer.
This role requires:
* Execute MRP (Material Requirements Planning) runs.
* Analyze and manage material planning for complex Bills of Materials (BOMs).
* Create purchase requisitions and production work orders.
* Perform ongoing monitoring and control of procurement and manufacturing processes.
* Prepare and present status reports using various information systems.
* Collaborate with multiple interfaces across the organization to ensure smooth project execution. Position Details:
* Full-time position, Sunday-Thursday.
* Location: Be'er Ya'akov, Israel.

In this role, you will tackle one of the most critical challenges in high-performance networking: Power.

This is an opportunity to join a high-impact team at the ground floor of a subject that is becoming a top priority. You won't be writing RTL; instead, you will have a holistic impact on our next-generation switches by estimating, measuring, and debugging power across the entire chip. This is a role for an engineer who wants to grow into a power expert within the world's most innovative silicon environment.

What youll be doing:

Working with the design team to define power-aware architectural methodologies and drive power-conscious design decisions across the Switch architecture.

Leading the research, development, and implementation of Switch micro-architecture power optimizations.

Participating in silicon validation to debug power-related issues and define the chip power profile.

Your Career:
As a Senior Staff AI Software Engineer on our Generative AI foundation team, you will build AI agents and shared infrastructure that power GenAI capabilities across the company. You will be involved in the full software lifecycle, from fast-moving prototypes to production-grade systems, enabling CyberArks product lines to adopt agentic workflows safely and at scale. You will collaborate with product managers, researchers, and engineers to translate ideas into robust services, bringing a pragmatic mindset to experimentation, iteration, and operational excellence.
Your Impact:
Engage in the full software lifecycle, from fast-moving prototypes and POCs to production-grade, observable systems.
Collaborate with product managers, researchers, and engineers to translate ideas into robust services.
Work hands-on with leading LLMs and the modern agentic ecosystem, leveraging a wide range of AWS services.
Use cutting-edge frameworks and techniques to develop, evaluate, and continuously improve solutions.
Implement solid design, flexible implementation, strong telemetry, and production feedback loops.

Our team in Yokneam, Israel is looking for a Senior Power Integrity Engineer to join the Hardware Board Design team and lead PI development of next-generation Network Adapters for high-speed communication products. Our Networking division delivers end-to-end InfiniBand and Ethernet connectivity for servers and storage, including adapter cards, switches, cables and software that power data centers, cloud, big data, Web 2.0 and high-performance computing workloads.

What you'll be doing:

Lead PI definition and implementation for board-level designs, from concept and architecture through validation, qualification and release to production.

Define the power core architecture and requirements and serve as the technical lead for all power-related performance and debug activities

Work closely with power supply vendors to align solutions with our product needs, and build and optimize configuration files for programmable regulators.

Own power delivery network (PDN) design for complex network adapter boards, including rail partitioning, decoupling strategy, VR selection and dynamic load support.

Perform system-level power integrity simulations (frequency and time domain) and co-simulation of circuits and PDN models to predict noise.

Create and maintain board PI design guidelines: stackup, materials, breakout, routing, decoupling and placement rules for layout teams and external partners.

Use advanced 2D/3D EM tools to model and optimize vias, planes, connectors, sockets and other interconnect elements for power integrity.

Perform lab characterization and correlation using VNA, TDR and high‑bandwidth oscilloscopes; refine models and design rules based on measurement data.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

We are looking for a senior Mechanical Engineer to join our mechanical engineering department as a key player in the development of next generation Network products. This key position includes leading the product and fixtures design, close interaction with HW, PMC (Product management & configuration), NPI, Thermal, Layout, Quality and Supply chain groups.

What you will be doing:

Drive multiple early design concepts while working in fast-paced product development cycles.

Independently lead product design from concept, through detailed design, and support it during Qualification, NPI and MP stages.

Join and lead task forces to investigate and support production excursions, failure analysis and reliability issues.

Collaborate in research of groundbreaking technologies, materials, and processes with other groups to bring in creative ideas that solve ever growing needs.