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we are looking for a 100% hands-on Storage services software engineer to join the block Storage group. you will be a member of a team that builds the next generation block Storage capabilities. you will work closely with a variety of teams and architects including the networking team, and external customers. you will take part in defining the software architecture and implementation of the most advanced Storage services! services that will need to meet extreme performance and scalability demands! we have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform of tomorrow.
at our company, we work, think and learn as a team. we thrive in a deeply strong environment, and we're passionate about a culture that demands innovation and the highest standards. the rewards are sweet and include collaborating with some of the smartest people in the industry, an aggressive compensation plan that rewards top performers, and the opportunity to work on products that transform the way people work and play.
what youll be doing:
100% hands-on coding role in C language, Kernel and userspace
research, design, implement and TEST, new and existing, distributed Storage services and features of our block Storage solution, in both host and dpu environments.
acquire understanding of the algorithms, the technicalities and the interaction with other components across our block Storage ecosystem.
analyze and solve challenging bugs and customer cases in large scale production systems, identifying issues in our or inbox Kernel modules and often in other components. drive new solutions based on any issues that arise

conduct in-depth performance characterization and analysis on large multi-gpu and multi-node clusters.
study the interaction of our libraries with all hw (gpu, cpu, networking) and sw components in the stack
evaluate proof-of-concepts, conduct trade-off analysis when multiple solutions are available
triage and root-cause performance issues reported by our customers
collect a lot of performance data ; build tools and infrastructure to visualize and analyze the information
collaborate with a very dynamic team across multiple time zones

we are looking for a formal Verification engineer for our nvidia networking team!
this is an exciting opportunity to join a hardworking pre-silicon design and verification team, working on groundbreaking switch technologies. we deploy state-of-the art formal verification tools and methodologies to prove design correctness. working in our formal verification team will expose you to a wide range of cutting edge design and technologies. our switch team delivers world class bridge and router solutions for hpc, data -center, network, and Storage markets. we micro-architect, verify, and deliver smart and high bandwidth multi port switches. nvidia has the most sophisticated formal tools and methodologies in the industry, which help us achieve a0 design tapeouts. as part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
what you'll be doing:
in this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
you will work on ambitious designs along with our pre-silicon team and take part in developing the next generation of core technology.
you will work on developing new formal verification methodologies and tactics.

looking for outstanding chip design Verification engineers to join our networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company. 
what you will be doing:
join tel aviv group, working in a combined design and verification team which develops phy layer ip within the networking silicon.
build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
work closely with multiple teams within organizations such as architecture, micro- architecture, fw and post-silicon validation.

we are now looking for a senior chip design engineer to join our switch silicon team. as a chip design engineer networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! 
what you'll be doing:
work in a design/verification team which develops core units within the switch silicon.
micro-architecture of rtl verification environments planning for units and modules.
design rtl of units/blocks according to arch. specifications under challenging constraints with high orientation to power, area, and performance.
rtl synthesis, timing, supporting verification, and silicon post to activities.
work closely with multiple teams within organizations such as architecture, u-arch, full chip micro-architecture, be, and fw.

we are now looking for a best-in-class Verification engineer to join our outstanding gpu-networking silicon engineering team. as a dv engineer at gpu-networking group, you'll make a real impact in a dynamic, technology-focused company while being a part of the team that develops the flagship product of todays semiconductor industry - gpu super-chip. 
what youll be doing:
work in a dv (design verification) team that has a global responsibility over deliverable units and clusters to the silicon gpu
integrations and full-chip models
verification of chip blocks/entities according to specifications under challenging constraints
ramp-up and run dv tasks on emulation platform

we are seeking a highly motivated high-performance system architect to join our team of experts and help shape the future of high-performance and ml / ai computing. our next-generation nvl systems will be at the forefront of connecting and powering the world's most advanced compute clusters, which would be used to train the most advanced ai models such as gpt and deepseek. as a high-performance system architect at nvidia, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.
what youll be doing:
define the nvl system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).
research various of solutions to enable the next large-scale-high-performance computing clusters. the position spans over various layers from algorithms, software, firmware, and hw.
collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

we are looking for a senior chip design Verification engineer for developing the next generation dft technologies.
as a senior chip design Verification engineer in the dft team , you will verify the design and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and complex products. our dft solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for verification of the dft design, architecture and micro-architecture using sophisticated verification methodologies.
as a member of our dft verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (testbenches, bfms, checkers, monitors), execute TEST /coverage plans, and verify the correctness of the design.
collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

our company has been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. its a unique legacy of innovation thats fueled by great technology-and amazing people.
today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world. doing whats never been done before takes vision, innovation, and the worlds best talent. as an our employee, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. come join the team that is building ai platform for operating ai factories to make a lasting impact on resilient operations of ai clusters.
what will you be doing:
you will bring together and understand internal and external customer requirements to improve ai cluster resiliency and design aiops-based solutions that address these needs.
develop automated workflows for issue detection and root cause analysis and closely collaborate with operators to debug sophisticated, Full-Stack ai cluster problems. we will bring to bear the findings for product improvements!
deliver compelling technical presentations and lead hands-on demos or training. you'll also handle evaluation deployments (poc/pov) and ensure smooth, reliable installations by staying engaged and encouraging throughout the customer journey.

as a Senior Software Architect in the gpu networking architecture team, you will define software defined networking architectural solutions. you'll also be part of a team of specialists who span across numerous technological fields related to the modern data center, such as distributed ai and deep learning systems, networking operating systems, virtualization, Storage, and more.
what youll be doing:
define system and software architecture for software defined networking (sdn) of ground breaking emerging ai networks which involves innovative software and hardware.
be an active member in setting the use-cases and metrics for monitoring complex high-speed networks control-plane.
work closely with various groups within nvidia to bring ai network technologies to reality, including gpu and switch hw and sw teams, product as well as fellow architects.

As a Mechanical Design Engineer, you will be responsible for the design, development, and validation of mechanical components and systems for our diverse product line, focusing on innovation and manufacturability. This role offers the opportunity to contribute directly to the advancement of sustainable energy solutions. Responsibilities:
* Design and develop robust and reliable mechanical solutions for electronic packaging, particularly for high-power outdoor products, considering thermal management, environmental protection, and manufacturability.
* Design components optimized for various manufacturing processes, including plastic injection molding, die casting, extrusion, and sheet metal fabrication.
* Collaborate with electrical engineers on the mechanical integration of printed circuit boards (PCBs) within product enclosures.
* Create and maintain detailed production documentation, including mechanical drawings, assembly instructions, and PCB layouts, ensuring accuracy and completeness.
* Review First Article Inspection (FAI) reports, analyze results, and approve parts for mass production, ensuring adherence to quality standards.
* Perform engineering calculations (e.g., stress analysis, heat transfer analysis, magnetic simulations, dynamic analysis) to validate designs and ensure performance requirements are met.
* Participate in design reviews, contribute to problem-solving, and drive continuous improvement in design processes.
* Collaborate with cross-functional teams, including product management, manufacturing, and testing, to ensure successful product development and launch.
* Contribute to the validation, testing, and troubleshooting of mechanical components and systems throughout the product development lifecycle.
Country:
Israel
City:
Herzliya

we are currently seeking a power integrity engineer. you will collaborate closely with our teams in the usa and india, drawing on extensive knowledge, technologies, and tools. as part of our team, you will contribute to the development of our ethernet switch system product line, supporting the process from concept through design, implementation, verification, and release to customers. if you enjoy working with talented individuals to achieve ambitious goals, nvidia could be the ideal place for you. our team is dynamic, working with cutting-edge and unique technology. if youre someone who thrives on challenges, we invite you to join this diverse team and make a significant impact!
what you'll be doing:
ensuring robust power integrity in physical design to optimize power delivery
design and optimize physical design solutions for power integrity. 
perform power integrity analysis and mitigation. 
focal point for pi for partitions owners.
collaborate with hardware and design teams on power delivery strategies.
utilize tools and flow in advance technology to meet project development

looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.

looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.

we are now looking for a senior chip design engineer to join our switch silicon team. as a chip design engineer at our networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
work in a design/verification team which develops core units within the switch silicon.
micro-architecture of rtl verification environments planning for units and modules.
design rtl of units/blocks according to arch. specifications under challenging constraints with high orientation to power, area, and performance.
rtl synthesis, timing, supporting verification, and silicon post to activities.
work closely with multiple teams within organizations such as architecture, u-arch, full chip micro-architecture, be, and fw.