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As a member of our CAD team, you will architect, develop, maintain and improve physical design verification (PDV) flows. The role requires you to work on flow and run-set development for various technology nodes and tool sets. Working alongside the CAD team, you will be collaborating with the custom digital/analog/mixed-signal design, physical design (PD) and chip integration teams. You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modify existing ones. Also, you should have worked with Dummy Metal Fill generation and Design for Manufacturability (DFM) rules at different technologies.
Responsibilities
Develop, improve and maintain all aspects of physical verification flow and methodology
Coordinate the effort of validating flows, improving for custom checks and data generation
Work with the design and PD teams to facilitate the chip design process
Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs
Collaborate with tool vendors and foundries for PDK performance enhancements

We are looking for a software engineer with strong backend skills, a product mindset, and the curiosity to bring LLM-powered agents into the toolchains and Linux environments where chips are actually designed. Success in this role means owning the agentic infrastructure end-to-end: from the platform our agents run on, to the integrations that let them safely act inside our customers' existing flows.
Description
You will join a growing team of ML and software engineers building GenAI solutions for chip design teams. In this role, you will:

* Architect, build, and operate the agentic infrastructure our team relies on:including LLM orchestration, tool-calling layers, multi-agent workflows, and the services that host them.
* Design and implement software solutions for chip design engineers, translating their workflows into reliable, automated agent-driven systems.
* Integrate our agents and services with existing Linux-based environments, in-house tools developed by the team, and third-party EDA tools.
* Manage agentic and ML workflows in production to ensure performance, high availability, and resource efficiency.
* Deploy and maintain production services, with proactive monitoring to catch quality and infrastructure regressions before they reach users.
* Build automated evaluation frameworks to measure retrieval quality, agent execution, and LLM output accuracy across releases.
* Partner with CAD teams to integrate pipelines and agents into CI/CD, ensuring reliable deployments and safe rollbacks.
* Implement access controls, authentication, and secret-handling practices appropriate for working with sensitive design data.
* Collaborate closely with ML engineers, researchers, and our customer teams.

As a Silicon Validation/Emulation Design Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators, as well as multiple ARM-based sub-systems. You will be a key contributor in our pre-silicon hardware validation efforts using Cadence Palladium emulation platforms, enabling early system integration and hardware validation. You will work closely with SoC architects, RTL designers, and verification engineers to ensure our designs are thoroughly validated before tape-out. You will help define the processes, methods, and tools for emulation environment development and debug of large complex SoCs.
If you enjoy a fast-paced and ambitious environment, collaborating with people across different functional areas, and thriving during crisis times, we encourage you to apply and join us!
Description
Building and maintaining Palladium emulation environments, including compile flows, netlist preparation, memory modeling, and clock/reset configurations.
System-level debug and root cause analysis of complex hardware issues on the emulation platform.
IP-level debug and validation, working closely with IP owners to isolate and resolve design issues.
Development and implementation of automation aids, flows, and scripts to improve Palladium build efficiency, debug turnaround, and platform utilization.
Performance profiling and optimization of emulation models to maximize execution speed.
Collaboration with multi-disciplinary groups to make sure emulation deliverables are on schedule and support critical program milestones.
Responsibilities
Own and maintain Palladium emulation build flows for SoC and subsystem-level models
Drive debug and triage of emulation model issues, working with RTL designers and verification engineers
Support system-level hardware validation efforts and hardware integration
Develop reusable debug methodologies and collateral to accelerate issue resolution
Optimize emulation model performance through compile tuning, partitioning strategies, and platform configuration
Thoroughly document flows, debug procedures, and best practices
Collaborate with cross-functional teams to define emulation requirements and support prototype hardware validation

We are seeking a highly motivated architect to join our team of experts and take part in shaping the future of high-performance ML / AI computing. Our next-generation Spectrum-X, InfiniBand and NVLink systems will be at the heart of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today. As a system/software architect, you will have the opportunity to work on some of the most innovative technology that is currently driving the world forward.

What youll be doing:

Define the next generations of Spectrum-X, InfiniBand and NVLink SW architecture.

Research of various solutions by defining and running POCs, evaluate SW and HW impact and conveying the solution architecture to the relevant teams. The solutions can span over various layers: from algorithms and high level software to firmware and HW.

Collaborate with multi-functional teams, including other architecture teams, VLSI logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

abra professional services is seeking a Project Manager! We are looking for an experienced Technological Project Manager to lead end-to-end development and implementation of AI solutions within a complex, multi-interface technical environment. This role requires a unique combination of technical and architectural understanding, strong client- and business-facing skills, and the ability to manage and drive development teams and vendors. Key Responsibilities
* Lead technological projects from business requirement identification through definition, architecture, development, testing, deployment, and adoption.
* Translate business needs and objectives into functional/technical specifications and actionable development tasks.
* Drive projects focused on AI technologies, including integrating AI solutions into organizational workflows and legacy/enterprise systems.
* Work closely with system architectures, integrations, APIs, and cross-system interfaces.
* Oversee day-to-day execution in Jira—managing backlogs, sprint planning, task prioritization, dependencies, status updates, and progress tracking.
* Maintain ongoing communication with business owners and clients, managing expectations, requirements, and executive status reporting.
* Motivate and coordinate cross-functional development teams, internal departments, and external vendors to hit deadlines and deliverables.
* Concurrently manage multiple projects and interfaces, proactively identifying risks, bottlenecks, and mitigation strategies.
* Oversee UAT testing, production deployment, and system integration.