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The Opportunity We are starting a new ML/AI organization directly reporting to the CTO, to pioneer next-generation capabilities for our industry-leading defense systems. As a Founding ML-Engineering Lead, you will be the technical cornerstone of this initiative. This is a high-impact role designed for a practitioner who seeks total technical ownership of the machine learning lifecycle. You will be responsible for taking novel AI projects from initial concept through data collection, design, implementation, and evaluation, all the way to deployment.

The Technical Challenge Our ML initiatives span a diverse technical landscape. You will lead projects that range from field-oriented applications, where high accuracy and reliability are paramount, to research-oriented tools and agentic workflows designed to enhance our R&D capabilities and accelerate complex data analysis. Working in deep collaboration with our R&D teams, you will leverage unique, proprietary data to solve problems at the forefront of the counter-drone industry.
What You Will Do:
End-to-End Ownership: Lead the full technical execution of ML projects, ensuring every stage-from data acquisition to deployment-meets our rigorous standards.
R&D Collaboration: Partner closely with R&D departments to design data collection strategies and integrate ML-based tools and agents into their specialized workflows.
Versatile Implementation: Develop models and intelligent systems for a variety of use cases, ranging from real-time field performance to autonomous research-support tools.
Technical Authority: Act as a founding voice for ML implementation and strategy within the CTOs office.

Required QA Automation Engineer
Your Mission:
The QA Automation Engineer will help to continuously improve the quality, reliability and end-user experience of various solutions delivered by our development team. Also, you will help efficiently deliver high-quality solutions to end users through the use of modern quality methodologies and test automation technologies combined with a streamlined release process. The individual must be forward-thinking and share in a common vision of quality, integrity and efficiency.
Responsibilities:
Define, write, maintain & perform manual & automated tests of multiple APIs, UIs & Web services for functionality, correctness and reliability
Maintain, expand and create automation solutions
Create, maintain and execute test, bug, story & other sprint board items in Azure DevOps
Analyze and understand functional and technical requirements to devise Test cases/Test scenarios that fully meets the testing scope to satisfy business/user/system requirements
Ensure prerequisites for testing are fully prepared, test data and test environment setup/configurations
Identify and log bugs during the Software Development life cycle till release to Production
Perform root cause analysis of the bugs and collaborate with the development team to resolve and test them
Work closely with the Support team to investigate and test customer and/or production issues.
Work with your lead on improving QA processes and practices and adhering to them to ensure that quality assurance standards are met.

The Business Application Analyst will be responsible for supporting the configuration, maintenance, and enhancement of our Netsuite ERP system to meet the evolving needs of our organization. By working closely with the team, the Analyst understand the business requirements, translate them into technical solutions, and drive continuous improvement initiatives within the Netsuite environment.

Key Responsibilities:
Gather, analyze, and update business requirements for Netsuite ERP systems enhancements and customizations.
Configure Netsuite modules, workflows, and dashboards to support business processes and improve operational efficiency.
Serve as the primary point of contact for Netsuite end-users, providing training, support, and troubleshooting assistance, as needed.
Conduct ongoing system testing, validation, and quality assurance to ensure accuracy and reliability of Netsuite data and processes.
Follow Netsuite updates, releases, and best practices to identify opportunities for system optimization and enhancement.
Review and document system configurations, processes, and procedures to support knowledge sharing and ensure system integrity.

We are currently seeking for a Mechanical Assembler, as a temporary position for 6 months (that may become a permanent position in the future), who will be responsible for the assembly of complex products using a variety of tools and/or equipment according to required specifications, processes, and procedures in a manufacturing environment.
This is a full-time position.

Responsibilities:
Read, comprehend, interpret and follow basic blueprints, diagrams, engineering drawings, specifications, and other written instructions and follow established procedures to accurately assemble products.
Cable preparation; including stripping, tinning and labeling.
Mechanical type assembly using hand tools and power tools.
Gluing and sealing using Loctite, epoxy, RTV and other compounds.
Working with various sized materials from heavy parts to small intricate parts.
Perform quality testing/inspecting to ensure the product meets specifications and quality standards.
Identify product defects and report on issues to appropriate personnel
Rework and/or repair assembled products according to engineering specification changes.
Keep accurate records/logs etc.
Handling of ESD sensitive materials and equipment.

Role responsibilities:
Final tests technician (Hands-on) in Production line.
Manage HW testing in production, Line setup, Calibration and Maintenance.
Deep HW knowledge in RF & Digital.
Functional testing of electronic circuits according to specifications.
Overall responsibility for debug & analysis in boards & System level.
Responsibility repair, analysis and documentation.
ATE stations technical support.

our companys innovative processors are designed into the advanced cellular systems of most tear-1 carriers .
We are looking for an experienced and creative Verification Engineer to join our Processor Verification Team.
In this role, you will be responsible for verifying the core units of our next-generation processors. You will work closely with the architecture and design teams to ensure functional correctness through advanced verification methodologies, taking ownership of verification environments from planning to coverage closure.

Define the AI core architecture that will shape the next generation of AI chips, leading the global competition in AI computing power. As a key contributor to the competitiveness of AI core architecture, we drive chip architecture innovation starting from algorithm evolution, building a full-stack closed-loop capability of "algorithm-architecture-circuit-system," and creating a globally leading, independently controllable AI accelerator core to support the Ascend AI ecosystem and the implementation of large model strategies.
Responsibilities:
Modeling of HW specification of new architecture and microarchitecture. Working closely with architect and microarchitecture on modeling the specification.

We are a highly experienced architecture group specializing in switch processing, with deep expertise in both hardware and software architecture in the high-speed networking domain.
Our innovative packet processors power some of the most advanced data centers in the world and are designed into tier-1 vendor platforms. With state-of-the-art technology, a strong track record of industry recognition, and multiple award-winning achievements, we continuously push the boundaries of performance and scalability.
Our group is involved across the entire development lifecycle - from early research and architectural definition to silicon production - working on both research initiatives and production-grade products.
our Impact
As HW Architect Team Leader, you will combine deep technical leadership with people leadership. You will shape next-generation networking silicon while building and mentoring a strong architecture team.
What Youll Be Doing
Lead, manage, and mentor a team of HW architects, fostering technical excellence and innovation.
Drive research, evaluation, and architectural definition of next-generation SoCs - from product requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet and NIC switches.
Lead system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate cross-functionally with design, verification, modeling, software, and other architecture teams to ensure end-to-end system alignment.
Identify and evaluate new technologies, methodologies, and architectural approaches for future products.
Provide technical direction, make key architectural trade-offs, and ensure execution excellence.

About the group:
We are a highly experienced architecture group specializing in switch processing, with deep expertise in both hardware and software architecture in the high-speed networking domain.
Our innovative packet processors power some of the most advanced data centers in the world and are designed into tier-1 vendor platforms. With state-of-the-art technology, a strong track record of industry recognition, and multiple award-winning achievements, we continuously push the boundaries of performance and scalability.
Our group is involved across the entire development lifecycle - from early research and architectural definition to silicon production - working on both research initiatives and production-grade products.
What will you be doing?
Lead research, evaluation, and architectural definition of next-generation chips - from requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet Switches.
Design the system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate closely with design, verification, and modeling teams to ensure architectural intent is fully realized.
Work cross-functionally with other architecture teams to shape cohesive system solutions.
Explore and evaluate new technologies and innovative approaches for future products.

our company, Huaweis Tel Aviv Research and Innovation Center, is looking for an experienced hands-on software engineer and compiler technology expert to join our Future-Computing-Infrastructure expert group. The group designs and develops technologies for the next-generation data center aimed at accelerating AI workloads for a unique HW, optimizing compute resource utilization and reducing data-center costs. Our projects involve hardware and software architecture co-design. They require high-level system understanding, creativity and innovative thinking.
If you want to be part of something bigger, if you are a team player with excellent communication skills and motivation to revolutionize data-center technology, youre welcome on board!
What will you be doing?
Complex static code analysis to determine possible bottlenecks and time-consuming operations within the code of AI model for inference
Architecture, design and implementation of compilation passes, compiling high-level languages to a unique HW
Take initiative to solve technical and business problems
Collaborate with other development and product teams in our company and in China to ensure the successful implementation and delivery of a solution.

We are currently looking for a Performance Simulation Expert develop and evaluate next generation performance features as well as develop the future generation of our Compute system simulation infrastructure, models and analysis tools
Responsibilities:
Develop and analyze performance and power features in our cycle accurate pre-silicon model and improve the accuracy of the current Server system simulator
Design the architecture of the new generation system simulation platform that will be used to analyze performance of Server (Compute and AI) workloads and identify performance bottlenecks
Develop new technologies, methodologies and tools for simulation. Analysis and debug of applications and workload on Huawei servers
Propose and simulate optimizations and innovations on the HW and SW in order to improve server performance for given workloads
Distribute the simulation platform, train and support other teams in China and in Europe using the simulation platform, technology and methodology.

Looking for a CPU performance modeling architect to take responsibility over the performance aspects of new CPU instructions or modes of operation. The role includes but is not limited to:
Partners with lead SW and HW architects to co-invent optimal HW and SW solutions that come to address requirements. Influences the direction based on experiments and simulation data
Models CPU functionality, performance and/or power in pre-silicon simulators
Defines and runs performance experiments to aid feature definition. Such experiments can be performed on a pre-silicon simulation environment or in a real system or on a combination of both or even in combination with analytical models
Provides experimental/proof of concept for new features and implementation alternatives meeting performance constraints.
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usages
Potentially (in the future), lead a team doing above activities
An adequately qualified candidate can also become the leader of definition for some features in addition to all the roles above.

Looking for a CPU Architect for codesign of HW/SW feature for our CPUs for cellphones and servers. The role includes but is not limited to:
Analysis of technical challenges and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Invents corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions (when applicable) in coordination with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts. (the HW/SW features are typically in the form of new instructions or of other Instruction Set constructs and belong to one of following domains: dense compute, general purpose accelerations, use case specific accelerations, system level instructions, Security related technologies, or instrumentation instructions.
Models CPU functionality, performance and power in simulators, analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.