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Required AI Data Engineer
About the role:
We're building the intelligence layer that lets everyone ask hard questions of our data and get trustworthy answers - in plain language, in seconds. As AI Data Engineer, you own the semantic and AI-native surface of our Snowflake platform: the governed semantic layer that defines "what a metric means," the Cortex Agents that let business users query it conversationally, and the infrastructure that keeps all of it fast, reliable, and ready to scale.
This is a builder-owner role. You'll ship the semantic models, wire up the agents, and set the standard for how analysts across the company work with data. You'll also lead the Data Analyst guild - the connective tissue that keeps our hub-and-spoke analytics model coherent as it grows.
If you're excited by the space where data engineering, LLM tooling, and analytics governance meet, this role sits right in the middle of it.
What youll Own:
Snowflake semantic layer - Own the semantic layer end-to-end as the single source of truth for metrics; design semantic models, enforce naming standards, and ensure consistent metric definitions across dashboards and AI agents.
Cortex Agents - Design and deploy conversational AI agents using Cortex Analyst and Cortex Search; tune for accuracy and safety, expose through multiple surfaces (Snowflake Intelligence, Streamlit, MCP), and build evaluation harnesses to maintain quality at scale.
Data craft (Analytics guild) - Co-lead the technical track of the Analytics guild; set SQL and modeling standards, run technical enablement and code reviews, and serve as the technical authority for analysts.
Scaling data infrastructure - Improve performance, reliability, cost efficiency, and governance across the dbt/Airflow/Airbyte/Snowflake stack as data volume and query load grow; optimize warehouse sizing, medallion layers, and ingestion pipelines.
What you'll do day to day:
Model and maintain semantic views that power both dashboards and AI agents, keeping definitions versioned, tested, and certified.
Build, evaluate, and iterate on Cortex Agents - including retrieval quality, guardrails, and observability.
Extend and optimize dbt models, Airflow DAGs, and Airbyte connectors across bronze/silver/gold layers.
Partner with GTM, Finance, CS, and Product stakeholders to translate business questions into governed, reusable data assets.
Run the Data Analyst guild: standards, reviews, enablement, and tooling.
Own data quality, lineage, and cost monitoring across the Snowflake platform.
Expose data and agents through Streamlit apps, BI tools (Omni), and MCP servers for internal AI workflows.

CodeValue is looking for a DevOps Engineer to join a large-scale government project in Jerusalem. The role combines Cloud & DevOps infrastructure, CI/CD, monitoring and logging, automation, troubleshooting, and infrastructure security , while working closely with development, infrastructure, security, DBA, networking, and architecture teams.

Were looking for a Hands-on AI & Data Engineering Manager to lead a team building intelligent, large-scale consumer experiences powered by AI. In this role, you will lead engineers developing AI-driven products, work closely with data scientists, product managers, and designers, and ensure that AI capabilities-from LLMs and agents to product data insights-are translated into reliable, scalable production systems. You will be responsible not only for delivering AI features, but also for analyzing product data and user behavior to continuously improve AI performance and product outcomes. This is a technical leadership role combining engineering management, architecture ownership, AI product development, and data-driven decision making.
Key responsibilities:
Lead a team of data scientists, data engineers and product analysts
Own the delivery of AI-powered product capabilities, from research and experimentation to production and operation
Drive excellence, code quality, and best development practices
Provide technical direction and hands-on guidance for complex AI systems
Drive the integration of LLMs, AI agents, and intelligent workflows into core consumer experiences
Ensure AI solutions are safe, scalable, observable, and continuously improving
Lead initiatives around product data analysis and experimentation
Analyze user interactions with product features to improve accuracy, UX, and business impact
Partner with product teams to define metrics, dashboards, and experiments that guide product improvements
Design system architectures for AI-enabled applications at scale
Evaluate and select technologies for AI platforms and data pipelines
Guide the development of prompt engineering frameworks and centralized prompt management
Ensure robust monitoring, evaluation, and feedback loops for AI outputs
Translate product and business goals into technical roadmaps and execution plans
Drive alignment between AI capabilities and measurable product outcomes.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Principal Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.
As an Principal Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.
Key Responsibilities
Emulation Flow Execution & Implementation
Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging
Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies
Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market
System-Level Debug & Validation
Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs
Ensure rapid cycles from RTL to functional stability through systematic debug approaches
Own technical blocks and drive them to completion independently
Cross-Functional Collaboration
Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios
Ensure seamless hardware-software integration for AI infrastructure connectivity
Collaborate with Design and Verification teams to optimize emulation strategies.

We are looking for a brilliant, curious, creative, and fun-loving Senior Automation Engineer with a passion for excellence and collaboration. Youll also be ready to take on a huge challenge of building and testing aprils applications, APIs, computation engine and financial platform! We are looking for an individual who is comfortable and excited about taking ownership and driving initiatives from beginning to end and is not afraid of anything (in tech :P). If youre all that and looking to lead, invent, and grow professionally you should definitely consider applying to join us on our journey!
Key responsibilities:
Design and develop aprils manual testing and automation processes, tools and infrastructure
Be part of our core engineering team developing our services and system architecture
Take significant part of the testing & quality assurance processes april-wide and ensure that quality is built into every step of the development life-cycle using the latest technologies and overcoming limitations
Help define and drive our best practices and frameworks
Work closely with the product team to define the testing strategy and incorporate it in our program plans and roadmap, execute the testing plans and be the advocate for benefits of QA & automation
Influence design decisions, architectures, select/evaluate tools, and enforce a quality-based approach.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.
As a Senior ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams
Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities
Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.
As a Senior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified
Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices
Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.
As an Senior Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.
Key Responsibilities
Emulation Flow Execution & Implementation
Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging
Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies
Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market
System-Level Debug & Validation
Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs
Ensure rapid cycles from RTL to functional stability through systematic debug approaches
Own technical blocks and drive them to completion independently
Cross-Functional Collaboration
Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios
Ensure seamless hardware-software integration for AI infrastructure connectivity
Collaborate with Design and Verification teams to optimize emulation strategies.

At Infinidat, a Lenovo company, we empower enterprises and service providers with cutting-edge storage platforms that redefine performance, reliability, and cyber resilience at scale. We are looking for a bright and motivated individual to join the Solutions Testing Group at Lenovo–Infinidat. As part of our Test Engineering team, you will collaborate closely with Product, Design, Development, and Customer Support teams throughout the entire product lifecycle. In this role, you will contribute to test planning and execution, combining hands-on manual testing with the development and maintenance of automated test frameworks across several of the company’s products. You will independently lead and deliver testing efforts end-to-end, from requirements analysis through final validation.

Responsibilities:

* Plan, design, and execute test strategies for complex products
* Perform manual and automated testing to ensure product quality
* Analyze test results and provide clear, actionable reports
* Develop advanced test scenarios using Python
* Maintain and enhance existing automation frameworks and test code
* Collaborate with cross-functional teams to ensure high-quality product delivery

We are looking for a Software Development Engineer to own the design and implementation of our inference data plane. We build the software that makes large models run efficiently on custom hardware - spanning model execution, memory management, data movement, and serving integration.
Our work covers the full inference path: integrating serving engines with custom hardware, developing high-performance compute kernels, enabling efficient data movement, and driving models from early validation through production. We operate at frontier scale with large distributed models.
This is a ground-up effort with rapidly evolving hardware and software. We need an individual contributor who can write and optimize low-level code for custom hardware, validate model architectures end-to-end, build test and profiling infrastructure, and drive performance across the stack.

Key job responsibilities
- Develop and optimize compute kernels for a custom ML accelerator architecture, targeting production-level performance for large language model inference.
- Implement and validate LLM architectures end-to-end - from PyTorch model definition through distributed execution on custom hardware.
- Integrate custom accelerator backends into open-source ML serving frameworks (vLLM, PyTorch), including scheduler extensions, memory management, and model parallelism.
- Build and maintain test infrastructure for model correctness validation across CPU, GPU, simulator, and hardware targets.
- Profile and optimize inference workloads - identify bottlenecks, instrument critical paths, and drive latency and throughput improvements from simulation through hardware bringup.
- Own features end-to-end: from design through implementation, testing, and integration into the broader software stack.
- Contribute to CI/CD pipelines that gate model and kernel changes on correctness and performance regressions.

We are looking for exceptional software engineers to help develop the next generation chips based on a revolutionary architecture.
In this job you will design and develop software for functional and performance validation.

In this role you will develop system level software, targeting chip architecture, functional correctness and performance, running on various platforms and validating chip functionality.