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Were hiring an AI Backend Engineering Manager to guide and grow a high-impact ML team driving AI-powered innovation across B2B SaaS platform. Youll lead the design and delivery of AI solutions while mentoring engineers and setting the technical direction for AI-first development at scale.
This is a leadership role with a balance of hands-on engineering and team management, perfect for someone who thrives on solving technical challenges, inspiring a team, and shaping the future of AI in fintech automation.
What You Will Do:
Lead & Mentor: Manage, mentor, and grow a team of AI/ML/Backend engineers, fostering technical excellence and career development.
Set Technical Direction: Define the ML strategy, ensuring best practices in architecture, frameworks, and operationalization.
Build and deploy AI-based solutions: Oversee the development and deployment of GenAI/LLM-powered solutions that address real-world challenges across products.
Scale & Operationalize: Establish scalable ML infrastructure, CI/CD, observability, and data pipelines for high-availability production systems.
Collaborate Cross-Functionally: Partner with product managers, engineers, and business stakeholders, clearly communicate progress, challenges, and outcomes.

We are seeking an experienced Principal Architect to lead the architecture of high-performance connectivity solutions, with a strong focus on PCIe, high-speed networking, and Ethernet-based systems.
This role will define next-generation architectures for AI infrastructure, working at the intersection of silicon, system, and protocol design. You will play a key role in shaping innovative solutions that enable hyperscale customers to build scalable, high-bandwidth, and low-latency systems.

This is a unique opportunity to join a new and growing Israel site, influence technical direction, and take ownership of critical architectural decisions impacting industry-leading products.

Key Responsibilities
Define and drive system and chip-level architecture for high-speed connectivity products.
Lead architecture for PCIe-based interconnects, networking protocols, and Ethernet subsystems.
Analyze system requirements and translate them into scalable and efficient hardware architectures.
Drive tradeoff analysis across performance, power, latency, area, and cost
Collaborate with cross-functional teams including RTL, Physical Design, Firmware, Validation, and Product Engineering.
Define and review micro-architecture specifications and ensure alignment across teams.
Contribute to standard-based and custom protocols for next-generation AI infrastructure.
Support performance modeling, simulation, and architectural validation.
Work closely with customers and partners to understand emerging use cases and requirements.
Mentor engineers and help build strong technical leadership within the Israel R&D center.

We are looking for a Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams.

Key Responsibilities
Perform hands-on post-silicon validation
Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability.
Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.
Drive complex issues from initial failure through root-cause analysis and final resolution.
Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.
Validate PCIe functionality across different generations, platforms, configurations, and operating conditions.
Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.
Develop automation to improve validation coverage, debug efficiency, and regression testing.

we are seeking a Full Stack Team Lead to drive AI-first development across our core platform.
As an AI-first company, we integrate artificial intelligence into every facet of our operations, from product development to internal processes. In this role, you'll lead a team of 5-6 dedicated full-stack developers, working on cutting-edge technologies to enhance user experiences and data-driven solutions.
You'll have the autonomy to make technical decisions and support other developers in a collaborative environment.
What You Will Do:
Lead Development Initiatives: Guide a team of full-stack developers in building core applications, ensuring the integration of AI-driven features.
Mentorship: Provide technical guidance to engineers, fostering their growth and promoting best practices in AI-assisted development.
Architectural Decisions: Make hands-on technical decisions for backend (Java + AWS) and frontend (React/Angular) components, incorporating AI tools where applicable.
Code Quality: Write clean, maintainable, and efficient code, setting high standards for code quality and review practices.
Cross-Functional Collaboration: Work closely with Product teams to prioritize features, estimate work, and keep projects on track, leveraging AI to streamline processes.
Innovation: Identify pain points and drive improvements in our codebase and processes, utilizing AI to enhance efficiency.
Team Motivation: Ensure daily alignment, remove blockers, and champion best practices within the team.

As we expand our presence in Israel, we are seeking a motivated Physical Design Student to join our founding local engineering team.

This is a unique opportunity to kickstart your career in the semiconductor industry. Working alongside senior industry veterans, you will gain hands-on experience in backend execution and advanced methodologies for cutting-edge chips that power the world's largest AI clusters. If you are passionate about silicon hardware, eager to learn, and thrive on solving complex engineering challenges, this role offers the perfect bridge between your academic studies and a high-impact career.


Key Responsibilities

Guided Implementation & Learning
Partner with and learn from senior engineers to support the physical implementation journey, including synthesis, floorplanning, Place & Route (P&R), and Clock-Tree Synthesis (CTS).
Assist in macro-level implementation and develop hands-on skills in complex layout routing.
Participate in deep-submicron process challenges under close professional mentorship.

Signoff & Design Integrity Support
Assist in running engineering checks for design integrity, including Static Timing Analysis (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR).
Learn to apply Logic Equivalence Checking (LEC) to help guarantee design correctness.
Gain exposure to the rigorous flows required to ensure first-pass silicon success.

Scripting & Cross-Functional Collaboration
Leverage and develop scripting tools to automate repetitive tasks and optimize the engineering environment.
Collaborate with Architecture, Design, and DFT teams to understand how different chip design disciplines intersect.
Actively participate in team reviews and technical discussions to ramp up backend methodologies.

Were hiring a ML Engineer to accelerate AI-driven innovation across B2B SaaS platform.
Youll be at the forefront of building intelligent systems that power core product experiences and automate internal operations, driving efficiency, speed, and scale across the organization. This is a high-impact, hands-on role in a fast-growing, AI-first company where machine learning is a foundational pillar, not a bolt-on feature. You'll partner with product, engineering, and operations teams to design and implement powerful ML and LLM-based solutions that make a measurable difference.
What You Will Do:
Build Intelligent Systems: Design and develop ML/LLM-powered solutions that solve real-world challenges across product and internal workflows.
Own Full Lifecycles: Take projects from concept all the way to production, including model training, evaluation, integration, and monitoring.
Leverage State-of-the-Art Tools: Work with leading frameworks like LangChain, Hugging Face, TensorFlow, and PyTorch to deliver cutting-edge functionality.
Collaborate Cross-Functionally: Partner with product managers, engineers, and stakeholders to embed AI capabilities into user-facing features and backend services.
Ship at Scale: Build and maintain scalable APIs and services, integrating best practices in CI/CD, observability, and cloud infrastructure.
Report with Impact: Share progress, challenges, and results clearly with technical and executive stakeholders.

We are hiring a Manager Design Engineer to help architect and deliver the connectivity silicon powering the world's largest AI clusters. You'll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.

This is a high-impact technical role at a hyper-growth company. You'll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap. If you want to ship silicon that defines AI infrastructure, this is the team.

Key Responsibilities

RTL Design & Implementation
Own RTL design for assigned blocks from microarchitecture through synthesis sign-off.
Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA.
Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality.

Cross-Functional Execution
Partner with architecture to translate specifications into implementation-ready microarchitecture.
Collaborate with verification on testplans, coverage closure, and bug triage.
Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure.

Technical Leadership & Quality
Mentor junior engineers and contribute to design methodology, scripts, and best practices.
Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments.
Drive structured, data-driven design decisions in support of aggressive tapeout schedules.

we are hiring a CX Manager with deep expertise in ERP finance systems, P2P workflows, and integrations.
This role is the ERP SME and integration owner within Customer Experience. The focus is to understand how finance processes work in customer ERPs, how they connect , and how to turn customer issues, bugs, feature gaps, and new requirements into clear integration solutions.
This is a hands-on role for someone who can solve complex customer issues, define ERP integration requirements for Engineering, and lead resolution end to end. The role also operates in a highly AI-enabled environment, using AI tools, platforms and agents to improve triage, analysis, escalation management, and communication.
This role owns ERP integration within Customer Experience: diagnosing customer issues, defining integration requirements, and driving resolution end to end.
Youll partner with teams in Israel and the US and report to the Director of Customer Experience.
What You Will Do:
Own ERP integration issues across bugs, feature gaps, and customer requirements.
Serve as ERP SME and L3 support lead for complex finance workflow and integration cases.
Diagnose setup, configuration, data flow, mapping, permissions, and sync issues.
Distinguish between customer setup issues, integration issues, and product issues, and drive the right resolution path
Define functional requirements and solutions for ERP integration fixes, sync issues, missing data flows, and new capabilities.
Lead escalations with strong ownership and clear internal/external communication.
Use AI tools to improve triage, analysis, RCA, summaries, and handoffs, with clear human-review checkpoints.

As we expand our presence in Israel, we're seeking a visionary Junior Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Junior Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution
Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing.

Signoff & Design Integrity
Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness.

Methodology Development & Cross-Functional Collaboration
Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation.
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity.
Leverage scripting and automation to make engineering environment faster and more robust.

We are looking for entrepreneurs with deep finance, fintech and ERP experience who bring strong product judgment.
This role is for people who have lived finance systems complexity firsthand and want to use that experience to build product. You might come from finance transformation, ERP, consulting, operations, or fintech. What matters is that you understand where workflows fall short, where controls matter, how better systems should work, and how product decisions create business value.
AI-native tools are part of how we build. This role is a chance to turn finance and ERP insight into product faster, with more context and better judgment than traditional product development allows. Youll collaborate closely with teams across the Bay Area and Israel.
What You Will Do
Find high-value opportunities in fintech and ERP workflows that should be redesigned, not just improved
Shape those opportunities into clear product direction with strong user and business value
Define workflow logic, edge cases, controls, exceptions, and handoffs
Decide what should be automated and what should remain human-driven
Work with engineering, design, data and marketing to build and ship new capabilities
Test ideas with customers, learn quickly, and refine fast
Own the path from problem identification to customer value and business impact

As we expand our presence in Israel, we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling our products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities
Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing.
Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration).
Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices.
Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints.
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance.
Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets.
Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp.
Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews.

As we expand our presence in Israel, we're seeking a visionary DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.

As a DFT Engineer, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.

Key Responsibilities

DFT Architecture & Strategy
Be part of the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support
Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards
Design and implement DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG for high-end devices

Test Pattern Development & Optimization
Generate and optimize high-quality test and debug patterns for production
Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
Drive test coverage and quality metrics to meet stringent manufacturing requirements

Cross-Functional Collaboration & Methodology Innovation
Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR
Participate in developing and maintaining cutting-edge DFT implementation flows
Automate and improve methodologies using advanced scripting and tools