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seeking a highly motivated and experienced Senior Software Engineer for a position focused on developing innovative network device monitoring and visualization solution.

Meet the Team

This position is part of Silicon One organization, based in Israel. Silicon One is the foundation of industry-leading networking hardware products, pushing the boundaries of technology and driving the next generation of high-performance, scalable solutions.

Your Impact

Design and develop visualization capabilities within our SDK environment
Lead the development of a brand-new comprehensive self-monitoring system for network devices from the ground up
Implement a comprehensive model for capturing and managing network state information
Drive cross-team collaboration and technical strategy
Work closely with senior technical leadership
Create and refine technical requirements and system designs
Build new systems and frameworks from the ground up

In this role, you will be part of the Silicon One Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
* Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
* Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.

* Handle all chip validation aspects, including:
* Building validation plans.
* Deloping ASIC software test infrastructure.
* Writing tests in Python/C++ over device SDK.
* Executing tests and analyzing results.

A leading technology company developing advanced multidisciplinary systems is looking for a QA Engineer to join its team.
The role involves hands-on testing of complex systems combining software and hardware, including TEST planning, execution, and documentation. Responsibilities:
Execute manual tests on Embedded systems, including GUI and hardware interfaces
Write TEST documents, TEST cases, and release notes
Manage defects and change requests throughout the development lifecycle
Perform testing in hardware-integrated environments (JIGs, cables, and measurement devices)
Support Quality Assurance processes and continuous product improvement

Define the AI core architecture that will shape the next generation of AI chips, leading the global competition in AI computing power. As a key contributor to the competitiveness of AI core architecture, we drive chip architecture innovation starting from algorithm evolution, building a full-stack closed-loop capability of "algorithm-architecture-circuit-system," and creating a globally leading, independently controllable AI accelerator core to support the Ascend AI ecosystem and the implementation of large model strategies.
Responsibilities:
Modeling of HW specification of new architecture and microarchitecture. Working closely with architect and microarchitecture on modeling the specification.

We are currently looking for a Performance Simulation Expert develop and evaluate next generation performance features as well as develop the future generation of our Compute system simulation infrastructure, models and analysis tools
Responsibilities:
Develop and analyze performance and power features in our cycle accurate pre-silicon model and improve the accuracy of the current Server system simulator
Design the architecture of the new generation system simulation platform that will be used to analyze performance of Server (Compute and AI) workloads and identify performance bottlenecks
Develop new technologies, methodologies and tools for simulation. Analysis and debug of applications and workload on Huawei servers
Propose and simulate optimizations and innovations on the HW and SW in order to improve server performance for given workloads
Distribute the simulation platform, train and support other teams in China and in Europe using the simulation platform, technology and methodology.

Looking for a CPU performance modeling architect to take responsibility over the performance aspects of new CPU instructions or modes of operation. The role includes but is not limited to:
Partners with lead SW and HW architects to co-invent optimal HW and SW solutions that come to address requirements. Influences the direction based on experiments and simulation data
Models CPU functionality, performance and/or power in pre-silicon simulators
Defines and runs performance experiments to aid feature definition. Such experiments can be performed on a pre-silicon simulation environment or in a real system or on a combination of both or even in combination with analytical models
Provides experimental/proof of concept for new features and implementation alternatives meeting performance constraints.
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usages
Potentially (in the future), lead a team doing above activities
An adequately qualified candidate can also become the leader of definition for some features in addition to all the roles above.

Looking for a CPU Architect for codesign of HW/SW feature for our CPUs for cellphones and servers. The role includes but is not limited to:
Analysis of technical challenges and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Invents corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions (when applicable) in coordination with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts. (the HW/SW features are typically in the form of new instructions or of other Instruction Set constructs and belong to one of following domains: dense compute, general purpose accelerations, use case specific accelerations, system level instructions, Security related technologies, or instrumentation instructions.
Models CPU functionality, performance and power in simulators, analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.

Looking for a CPU Architect with expertise in HW/SW codesign of dense computational logic (e.g., vector, matrix)
The role includes but is not limited to:
Analysis of technical challenges in relevant use cases and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Invents corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions in cooperation with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts.
(Preferably) models CPU functionality, performance and power in simulators.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.

We are looking for an experienced and creative AI processor VLSI Architect to architect and model the core of our next generation processors.

Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Micro architect will take charge in defining a processor Micro architecture features that will improve the performance and reduce the power consumption of the CPU core. This architect will use a performance simulator to explore his ideas and will analyze implementability of these features: Power, Timing, Area. This architect will utilize his processor and VLSI design experience to develop many advanced features for Huawei processors.

The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Architect will take charge of defining a processor on chip inter-connect and coherent fabric that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

We are looking for a skilled and motivated experienced rt systems integration & release manager to lead an systems integration team and own the end-to-end integration and release process for Real-Time Embedded products. this role is responsible for defining integration workflows, managing team execution, and ensuring that system releases are stable, predictable, and aligned with quality and delivery commitments.
the ideal candidate combines deep Embedded systems expertise, strong people leadership, and disciplined release and process management. what will your job look like:
directly manage and mentor a team of  rt systems integration and release engineers.
define, implement, and continuously improve the rt system integration and release management processes.
establish standard workflows, best practices, documentation, and quality gates.
ensure consistent execution of integration activities across projects.
drive alignment to integration processes across firmware, software, hardware, QA, and system validation teams.
identify integration risks early and implement mitigation strategies.
lead system -level integration of  Real-Time hardware and software.
manage system debugging, and root-cause analysis of complex integration issues.
oversee validation, verification, and system -level testing activities.
communicate progress, risks, and mitigation strategies to stakeholders and leadership.

we are the production TEST team - responsible for the definition, development, and deployment of production TEST operations for the worlds most advanced socs for adas and self-driving vehicles.
this is your opportunity to join a team during its initial forming stage and leave your mark as our company assumes full ownership for its silicon production operations to enable high volume manufacturing for cutting-edge automotive products. what will your job look like?
work closely with the design teams from early stages of the design process to review dfx architecture and define TEST requirements.
define TEST methodologies and generate TEST content for high-speed interfaces of Embedded ip blocks (lpddr4/5, pcie gen4/5, d/ C /mphy).
TEST program coding, pattern conversion and pre-si validation (virtual TEST simulations)
support load board and probe card design activities.
lead post-si TEST program debug activities to enable delivery of samples to internal and external customers.
TEST program characterization and tuning to enhance TEST program quality to meet automotive standards.
support quality & reliability team to enable effective and timely qual plan execution.
lead TEST deployment activities with tier-one foundry and osat vendors to enable large-scale wafer-sort and final- TEST operations.