The company Operating System Team is looking for a highly talented Embedded SW Integration Engineer with a passion for operating systems and Linux in specific.
The team is developing the Boot and Operating System SW for our companys autonomous vehicle and smart advanced driver assist platforms.
What will your job look like?
Hands-on debugging and testing of OS and related components (Boot, HW initialization, Device drivers, Linux Kernel, User space libraries and tools & automated tests in python).
Deep understanding of the involved OS/Boot components and their integration with other SW/HW modules involving testing automation and system level validation.
Closely work with members of the Boot and OS development teams to integrate, test and automate new features, components and systems.
Release & feature management in a multi-project and multi-disciplinary environment while managing CI systems for testing coverage.

The company Operating System Team is looking for a highly talented Embedded SW Integration Engineer with a passion for operating systems and Linux in specific.
The team is developing the Boot and Operating System SW for our companys autonomous vehicle and smart advanced driver assist platforms.
What will your job look like?
Hands-on debugging and testing of OS and related components (Boot, HW initialization, Device drivers, Linux Kernel, User space libraries and tools & automated tests in python).
Deep understanding of the involved OS/Boot components and their integration with other SW/HW modules involving testing automation and system level validation.
Closely work with members of the Boot and OS development teams to integrate, test and automate new features, components and systems.
Release & feature management in a multi-project and multi-disciplinary environment while managing CI systems for testing coverage.

We are looking for an Experienced HW SERDES Engineer to join Annapurnas SPIV (System Platform Interface validation) team.
As a member of the SPIV team, you will own End-to-end subset of system PCIe SERDES interfaces across range of products through product life cycle:
1. Validation and qualification.
2. Integration.
3. Deployment and post-deployment support.
4. Failure analysis.
5. Pre silicon activities for new technologies.
As owner, you will set the strategy for PCIe SERDES qualification over multiple platforms, ensure the design worked well and drive complex system debugs involving HW and FW components.

You will define NPI practices and engage in pre-silicon efforts to explore new technologies and mitigate integration risks. You will enhance SERDES qualification results with large scale customer performance analysis to discover SERDES life-cycle issues and mitigate them.

This is a fast-paced, intellectually challenging position, and you will work with thought leaders in multiple areas of technology. We are changing industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today.

Key job responsibilities
- Approve future products PCIe SERDES technologies.
- Define new products SERDES qualification and validation strategy and lead the execution.
- Engage integrations of Annapurna Labs products with other vendors PCIe HW components.
- Support ongoing integrations of PCIe SERDES in new products.
- Lead triage, PCIe SERDES debug and root cause analysis of systems in AWS data centers.
- Drive and maintain training, quality documentation and collateral to improve in-fleet operation.

We are looking for a SoC / IP Architect to shape the next revolution in electronics!
Responsibilities
Define and design architecture: Create the overall SoC/IP architecture based on product and customer requirements and define detailed technical specifications.
Collaborate with cross-functional teams: Work with a variety of teams, including logic design, verification, firmware architecture and development teams, and physical design, to ensure successful execution.
Lead technical discussions and architectural reviews, guiding design and verification teams to deliver scalable, high-quality implementations.
System-level integration: Ensure seamless hardware-software co-design by working on aspects like control paths, interrupt schemes, and debug infrastructure.
Drive architectural decisions that optimize scalability, and future readiness for next-generation applications.

We're looking for a talented SoC Integration Lead to join our Nitro team and help shape what comes next. You will spearhead the SoC integration activities of sophisticated networking chips, collaborating closely with Architecture, RTL Design, Physical Design, Package Design, Verification, Software, DFT, and additional teams in a dynamic, open, and fast-paced environment. As a member of the Nitro project, you will have influence over the device through its entire lifecycle from product definition to mass production. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match, powering hundreds of thousands of businesses across 190 countries.

Key job responsibilities
Take full ownership of SoC integration, including IPs development, partitioning, clock domain crossing (CDC), reset domain crossing (RDC), exploratory synthesis, and design quality verification.
Drive chip-level design implementation by partnering with multiple teams including Architecture, RTL Design, DFT, Verification, System Verification, STA, and Physical Design.
Oversee the creation of SoC-level IP blocks such as fabrics, interfaces, and security modules.
Lead RTL integration activities including micro-architecture definition, RTL coding and debug, synthesis and timing closure, and sign-off.
Address diverse functional and structural challenges, encompassing functional debugging, physical design preparation, emulation, and design quality issue resolution.
Contribute to the creation and implementation of design flows and automated solutions that facilitate efficient SoC development.
Support Verification and Emulation teams through test plan development and coverage review.
Ensure the chip meets quality and reliability standards while delivering to physical design teams, emulation platforms, firmware developers, and other stakeholders.

we are looking for an Emulation Engineer to join our Radar VLSI team and drive the development of next-generation ASIC Sensors.
We are developing best-in-class automotive radar solutions to complement our companys autonomous driving platform. Joining our expert team, you will leverage our companys unique assets to work on cutting-edge technology in a dynamic and challenging environment.
What will your job look like?
In this role, you will build high-end Emulation environments based on new designs. The position involves building and integrating complex components, working with cross-functional engineering teams, and developing systems that will change the way we drive.
We are looking for an engineer who thrives on challenges and is committed to engineering excellence while navigating complex constraints.
Lead Emulation development for the VLSI team.
Work closely with SW, Logic, and Verification engineers.
Serve as an expert matter for your domain, with full responsibility for driving and implementing improvements and new ideas.

We are looking for a System Engineer with Software Engineering background to be part of defining, shaping and integrating solutions to next generation of our cloud platforms.

We are looking for an exceptional engineer to own the development, testing, and monitoring of the manufacturing health of Amazon Graviton server products. You will be part of a team integrating new silicon, hardware, firmware, and software into a revolutionary system architecture.

Key job responsibilities
Lead triage, debugging, and root cause analysis of systems in our data centers.
Enhance troubleshooting capabilities and drive closure of in-fleet problems.
Analyze customer workflows and requirements to provide targeted resolutions.
Collaborate with Annapurna Labs monitoring team and root cause teams to improve product quality and reliability in fleet operations.
Represent the customer voice by providing fleet operation insights and requirements to Annapurna Labs' ASIC design, software development, QA, and architecture teams.
Develop and maintain training materials, quality documentation, and collateral to improve in-fleet operations.
Design and implement tools and scripts to support projects and customize solutions based on requirements.
Travel as needed, approximately 2-4 times per year.

We are seeking talented, creative and disciplined engineers to join the best-in-class team that plays a significant part in the development of new silicon for our eco-systems by engaging in a dynamic, highly collaborative environment. As a Wireless MAC System Architect, you will be a core member of our highly innovative and visible Wireless System-on-Chip (SoC) design team that defines modem architectures, develops MAC-layer algorithms, and invents embedded DSP algorithms for chips enabling exciting new wireless applications. You will be responsible for developing state-of-the-art wireless SoC products that are enjoyed by millions of our customers. Application areas include ultra-wideband sensing and specialized wireless audio; products enabled or improved by our teams SoCs include specialized audio headsets (such as AirPods), watches and iPhones.

In this role you will be responsible for the architecture of the Connectivity IP with focus on the MAC sub-system: - Define, document and Spec Connectivity MAC architecture and performance requirements.
- Analyze & simulate the performance of the Connectivity IP in real-life use-cases, achieving benchmarking performances in several metrics, including Throughput, Robustness, Co-existence with other Wireless IPs and more.
- Working closely with other architects (PHY, Power Management, FW and SW) to introduce best in class Connectivity IP solution.
- Develop innovative system architectures and protocols to deliver best-in-class performance for the MAC subsystem of custom wireless silicon solutions.
- Introduce cross-domain features where opportunities exist for innovation to achieve enhanced performance.
- Produce MAC architecture, specifications and corresponding performance/reference modeling in support of digital HW and FW design and verification efforts.
- Develop and maintain a MAC systems infrastructure applying the best methodologies for system-level simulation, pre-silicon prototyping (including emulation and FPGA prototyping), FW QA, regression and MTBF testing, and system verification to ensure first-time design success.
- Support the delivery of new wireless technologies to the Product Systems teams.

As a System Integration Engineer on our DDR team, you'll own end-to-end interface development and integration across the full product lifecycle - from early concept through silicon bring-up to production debugging at scale. You'll be part of developing the advanced memory technologies that power our AGI fleet.

Day-to-day, you will:
1. Shape interface design strategies - influence architectural decisions that define next-generation memory subsystems.
2. Drive system integration - bring together hardware, firmware, and software to deliver optimal design implementations.
3. Debug at cloud scale - leverage data from the world's largest public cloud to solve complex cross-domain challenges.
4. Collaborate with industry leaders - work directly with the top DRAM manufacturers in the world.
5. Raise the bar - set quality standards and drive continuous improvements in performance, reliability, and cost.

our company's EyeQ Platform Group (EPG) is seeking a motivated Formal Verification Engineer to join our team and contribute to development of hardware verification environments.
This position offers an opportunity to apply formal methods to verify the correctness of various complex digital systems.
This is an exciting opportunity to join a team of talented engineers, working cutting edge technologies in the field of autonomous vehicle.
What will your job look like:
Be the owner of formal verification environment from first draft to sign-off stage
Apply formal methods to verify the correctness of various complex digital systems
Work with HW architects\designers to define assumptions, rules and cover properties
Help define the formal verification methodology and environment to be applied by the team
Explore new Formal methods and Tools
Work with tools like Cadence JasperGold, Verisium manager, Xcelium, Indago
Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues
Develop generic formal blocks\functions of commonly used logic, to be later used off the shelf.