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seeking an experienced software engineer to join the networking switch sw group, developing the switch operating system (nvos). key role in developing the nvos is critical for next-gen networking tech for hpc data centers. are you passionate about working on innovative technologies? then we want to hear from you!
what you'll be doing:
owning and leading the nvos including development, testing flow and product life cycle.
as a senior software engineer at nvidia, you will use your expertise in C ++ and Python to develop nvos features and support new products.
lead nvos integrations with fw, hardware, and production teams.
support internal and external customers for any nvos related items.

we are now looking for a motivated chip architect to use your creativity to work on the connectx network adapter with the highly inventive and knowledgeable team.
what you'll be doing:
define the network adapter chip architecture end to end from the market requirements through design and all product life cycles (post/pre-silicon, on deployments). work with related industry standards & customers on deploying your tech.
collaborate with teams across teams (physical design, logic design, system software, firmware, applications)
work on proof of concepts and advance development projects.
perform research and analysis for current and future architectures.
craft product design specifications.
serve as a focal point within the organization and distribute the knowledge that you acquire.

seeking a highly skilled and modern software engineer to develop and prototype brand new advancements in distributed training and inference using nvidias spectrum-x ai fabric. this role offers a rare chance to pioneer ai and networking technology, contributing to ground-breaking projects that will define the landscape of large-scale ai systems. improve ai app-networking connection by refining communication, crafting congestion control, coding nic firmware, and expanding switch sdk features for enhanced ai factory efficiency. your work impacts large ai system development, scaling, and speed.
what youll be doing:
prototype end-to-end solutions to improve distributed training and disaggregated inference performance.
analyze and optimize communication flows across application, transport, and network layers.
develop system software spanning communication libraries, drivers, and firmware integrations.
collaborate with hardware, firmware, and sdk teams to co-design network features.
validate and integrate prototypes into nvidias ai infrastructure and products.

we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
what youll be doing:
you will be in charge of state of the art design for TEST /atpg flows and implementation
take full atpg ownership end to end on a project, from arch & planning to pattern generation, verification and post silicon bring up and diagnosis.
inventing and maintaining automation flows that provide the short TEST time to production

we're looking for a hardware architect for our nic and dpu division. in this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of nvidias next generation nic and dpu products. your role will be cross-disciplinary, working with software, asic design, verification, physical design and platform teams to improve performance and debug.
what you'll be doing:
learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and Verification engineers.
define the implementation of the most sophisticated debug features of our next products, balancing architecture requirements with backend, execution, and design considerations.
define the implementation of debug capabilities to support performance validation and improvements
understand our system debug requirements and help define the por of our nic and dpu product line.
face the most challenging full-chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.
work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.
thoroughly understand SOC flows, pcie, ethernet, infiniband and nvlink protocols.

we are now looking for a senior hpc site reliability engineer to join our mission and continue improving our hpc infrastructure. a meaningful part of nvidias strength is our unique and advanced development tools and environments that enable our incredible pace of innovation. we are looking for architects to help us evolve the way our private compute cloud is architected and optimized. 
what you will be doing: 
provide leadership in the design and implementation of our large-scale compute cloud that enables the world's top chip modelers, designers, and deep learning experts to invent groundbreaking technology.
identify architectural changes or completely innovative approaches in our cloud architecture and design. 
help with strategic challenges we encounter, including: effective resource utilization in a heterogeneous compute environment, evolving our private/public cloud strategy, capacity modeling, and planning for multi-year growth and scaling across our global computing environment!

looking for an hpc and ai data center engineer to join the networking cloud solutions hpc/ai infrastructure team. we are focused on building supercomputers and hpc clusters based on groundbreaking technologies. we are looking for a lab manager, be a key player to the most exciting computing hardware and software to contribute to the latest breakthroughs in artificial intelligence and gpu computing. take part of building large-scale compute and deep learning software and hardware platforms, work together and support many scientific researchers, developers, and customers to craft improved workflows and develop new, leading differentiated solutions.
what you will be doing:
plan and build complex cluster and supercomputers in various of data center and labs
rack stack and cable management to ensure efficient use of space and easy maintenance
ensure data centers and labs power and cooling efficiency while optimizing rack space utilization
data centers and labs daily operation and support
installations for variety of infrastructure and solutions - cloud, vms, Storage, network, hpc and ai
perform troubleshooting - network, optic cabling, bare metal, operating system.
support research & development activities

join our growing software architecture research team. the ideal candidate will be conducting cutting-edge research at the intersection of networking, security, and communications, and working alongside top experts in these fields. with incredible resources in networking, you will be able to impact, contribute and advance these domains for scalable accelerated computing. topics include but are not limited to remote direct memory access, hardware offloading and hardware acceleration, distributed accelerator networks, ai for networking and security, Storage management, cryptography accelerators and architecture. with its unique open culture, nvidia is one of the best industry labs to do accelerated computing research.
 
what youll be doing:
develop novel hw architecture models
simulations ranging from specific components to complete data center environments
develop sdks for novel hw capabilities
designing and implementing services, runtime systems, and applications over sdk
evaluate and optimize application performance
partner and collaborate with other forward-thinking team members and external researchers
participate and speak at conferences and events
work with intelligent networking machines powered by ai systems that can learn, reason and interact with other network components

as a senior architect in the advanced development team, you will explore technological challenges on accelerate networking and building ai data centers. research new transport functions and semantics for optimizing ai workloads. you will also be leading architectural and development efforts across numerous technological fields, related to the modern data center, such as distributed ai and deep learning solutions, data analytics, high performance computing (hpc), software defined networking (sdn), virtualization, Storage, and more.
what youll be doing:
enhance gpu networking offerings for accelerating ai workloads, such as dynamo or nvidia nixl.
identify and evaluate new technologies, innovations and partner relationships for alignment with our technology roadmap and business value.
lead architecture and design of such technologies.
lead proof-of-concept development to evaluate and drive such technologies.

our team in israel is looking for a dedicated chiplet sta owner to join us in defining the next era of ai's networking. this is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. if you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!
what you'll be doing:
perform advanced static timing analysis (sta) at chiplet and fc level.
running prime time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
identify convergence risks and work closely with physical design, rtl and dft teams, ensuring convergence throughout various project stages.
responsible for a full timing closer and quality approval from pre-layout sta model through signoff.

we are looking for a power u-arch senior engineer. our company is known as a world leader in providing energy-efficient high-performance products and we continue to invest in the research and development of hyper-efficient SOC architectures. we are continually innovating in creative and unrivaled ways to improve our ability to deliver exceptional perf/watt solutions in a wide range of sectors and verticals. come join our applied power team to develop state of the art dpu products.
what you'll be doing:
lead a micro-architecture of power features such as: power management, logical power features, etc
work with dpu arch team on power features definition.
understand the workload characteristics for dpu workloads at system scale to drive new hw/sw features.

we are looking for best-in-class physical design power engineer to join our outstanding networking silicon power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best power! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you will be doing:
power optimization of physical design, of blocks/top-level/fc under challenging constraints.
optimization involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.
power estimation and power modeling.

we are hiring a skilled senior dpu performance Validation engineer for our dpu product lines. this includes chip architecture performance characterization, debug, and validation across single-die and multi-die systems. working in the network silicon engineering group, you will be responsible for debugging, analyzing, and validating performance and functional behavior of current and future silicon devices. you will collaborate with chip design, verification, fw, and architecture teams to ensure successful product development with bold product cycles. the qualified candidate should be comfortable working in simulation and emulation environments, with strong skills in rtl-level debug, waveform analysis, and system -level performance root cause analysis.
what you will be doing:
learn and analyze system -level operation of dpus
debug and root-cause performance issues in pre-silicon environments, across rtl, waveform traces, and multi-die system simulations.
collaborate closely with design, verification, architecture, and performance modeling teams to isolate and fix issues.
develop and improve validation methodologies for performance experiments and data collection.
automate repetitive debug and validation tasks to scale coverage and efficiency.

we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
perform advanced static timing analysis (sta) for hsio at chiplet and fc level.
running prime time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
identify convergence risks and work closely with physical design, rtl and dft teams, ensuring convergence throughout various project stages.
responsible for a full timing closer and quality approval from pre-layout sta model through signoff.
ai use for timing optimization and data analysis.

we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
you will be responsible for chip floorplan and pin placement, ensuring integration within our innovative builds.
we expect you to run, debug, and approve physical verification flows across multiple projects, ensuring strict adherence to our high standards.
you will perform physical layout implementation, planning and optimization, contributing to the development of our groundbreaking chips.
we are widely considered to be one of the technology worlds most desirable employers. we have some of the most forward-thinking people in the world working for us. are you a creative and autonomous engineer who loves a challenge? are you ready to become the engineer you always wanted to be? come and be part of the best physical design team in the industry!