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5 ימים
חברה חסויה
Location: Yokne`am
Job Type: Full Time
we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
perform advanced static timing analysis (sta) for hsio at chiplet and fc level.
running prime time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
identify convergence risks and work closely with physical design, rtl and dft teams, ensuring convergence throughout various project stages.
responsible for a full timing closer and quality approval from pre-layout sta model through signoff.
ai use for timing optimization and data analysis.
Requirements:
b.sc./ m.sc. in electrical engineering.
at least 5+ years of hands-on sta experience.
experience in prime time and signoff methodologies.
a great teammate who thrives in a collaborative environment.
ai tools orientation or alternatively a desire to learn.
ways to stand out from the crowd:
agentic frameworks.
ai prompting experience.
experience in Linux environments.
tcl, Python, shell scripting abilities.
experience with data collection and analysis.
This position is open to all candidates.
 
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5 ימים
חברה חסויה
Location: Yokne`am
Job Type: Full Time
our team in israel is looking for a dedicated chiplet sta owner to join us in defining the next era of ai's networking. this is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. if you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!
what you'll be doing:
perform advanced static timing analysis (sta) at chiplet and fc level.
running prime time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
identify convergence risks and work closely with physical design, rtl and dft teams, ensuring convergence throughout various project stages.
responsible for a full timing closer and quality approval from pre-layout sta model through signoff.
Requirements:
what we need to see:
b.sc./ m.sc. in electrical engineering.
at least 5+ years of hands-on sta experience.
experience in prime time and signoff methodologies.
excellent leadership capabilities.
ways to stand out from the crowd:
knowledge in physical design flows and methodologies (synthesis, pnr, dft designs).
trong background of prime time tool.
great teammate.
This position is open to all candidates.
 
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22/03/2026
חברה חסויה
Location: More than one
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:
You will be responsible for complex physical design unit designs, ensuring integration within our innovative builds.
We expect you to run, debug, and approve PnR and verification flows across multiple projects, ensuring strict adherence to our high standards.
You will perform physical design implementation, planning and optimization, contributing to the development of our groundbreaking chips.
Requirements:
What we need to see:
B.SC./ M.SC. in Electrical Engineering
You should have at least 5+ years of hands-on Physical Design 'Place and Route' experience, demonstrating your proven expertise.
A strong background in Physical Design methodology, including Synthesis, Floorplan, CTS and Routing, is necessary.
Sign-off stages experince such as , 'STA', 'PV', 'LEC' and 'EMIR'.
In-depth knowledge of advanced silicon process technologies.
Familiarity with physical build EDA tools, including Synopsys and Cadence.
A great teammate who thrives in a collaborative environment.
AI tools orientation or alternatively a desire to learn.

Ways to stand out from the crowd:
AI prompting experience.
Experience in Linux environments.
TCL, Python, shell scripting abilities.
Experience with data collection and analysis.
Understanding of the chip and die verification process.
This position is open to all candidates.
 
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5 ימים
Location: Yokne`am
Job Type: Full Time
we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
you will be responsible for chip floorplan and pin placement, ensuring integration within our innovative builds.
we expect you to run, debug, and approve physical verification flows across multiple projects, ensuring strict adherence to our high standards.
you will perform physical layout implementation, planning and optimization, contributing to the development of our groundbreaking chips.
we are widely considered to be one of the technology worlds most desirable employers. we have some of the most forward-thinking people in the world working for us. are you a creative and autonomous engineer who loves a challenge? are you ready to become the engineer you always wanted to be? come and be part of the best physical design team in the industry!
Requirements:
b.sc./ m.sc. in electrical engineering
you should have at least 5+ years of hands-on layout experience, demonstrating your proven expertise.
a strong background in physical verification methodology, including erc, lvs and drc, is necessary.
in-depth knowledge of advanced silicon process technologies.
familiarity with physical build eda tools, including synopsys and cadence.
a great teammate who thrives in a collaborative environment.
ai tools orientation or alternatively a desire to learn.
ways to stand out from the crowd:
experience in Linux environments.
tcl, Python, shell scripting abilities.
experience with data collection and analysis
understanding of the chip and die verification process
This position is open to all candidates.
 
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5 ימים
Location: Yokne`am
Job Type: Full Time
we are looking for best-in-class physical design power engineer to join our outstanding networking silicon power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best power! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you will be doing:
power optimization of physical design, of blocks/top-level/fc under challenging constraints.
optimization involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.
power estimation and power modeling.
Requirements:
what we need to see:
b.sc./ m.sc. or equivalent experience in electrical engineering/computer engineering.
2+ years of experience in physical design and/or be power optimization aspects.
familiarity with physical design eda tools (such as synopsys, cadence, etc.).
knowledge in physical design flows and methodologies (pnr, sta, physical verification) is an advantage.
fe design experience is an advantage.
excellent problem-solving, partnership, and interpersonal skills.
our company has some of the most forward-thinking people in the world working for us. are you a creative and autonomous engineer who loves a challenge? are you ready to become the engineer you always wanted to be? come and be part of the best physical design team in the industry!
This position is open to all candidates.
 
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4 ימים
Location: Yokne`am
Job Type: Full Time
we are now looking for best-in-class senior chip design Verification engineer to join our outstanding network adapter silicon group, developing the industry's best high-speed smart communication devices, data processing unit (dpu), delivering the highest throughput and lowest latency! come and take a significant part in verifying and designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company. 
what you'll be doing:
work in a verification team which develops some of the networking silicon core units.
build reference models, verify and simulate chip blocks/entities according to specifications under challenging constraints with high orientation to performance.
gain a strong understanding of chip micro-architecture and features, and develop the verification environments.
work closely with multiple teams within organizations such as architecture, micro- architecture, and fw.
Requirements:
what we need to see:
b.sc. or above in electrical engineering or computer engineering.
5+ years of validated experience.
professional verification experience, knowledge in advanced verification methodologies and tools.
a team player with excellent communication and interpersonal skills.
strong debugging, problem solving and analytical skills.
demonstrates deep understanding in design and verification logic.
self-motivated, ability to work independently and drive tasks to completion. 
ways to stand out from the crowd:
prior design or verification experience of high-speed interconnects, smart nic and/or SOC.
experience in developing verification environments in Specman and/or prior knowledge in verilog.
knowledge in network protocols.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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4 ימים
חברה חסויה
Location: Yokne`am
Job Type: Full Time
we are looking for best-in-class senior full-chip Verification engineer to join our networking silicon team. in this role, you will be responsible for the development and verification of our next-generation nics at the system level. you will contribute to the architecture of high-speed communication devices by driving full-chip verification execution for the networking solutions powering the worlds most advanced data centers, enjoy working in a meaningful, growing environment where you make a huge impact in a technology-focused company.
what youll be doing:
full-chip verification & execution: own complex system -level features by defining verification plans and driving the end-to-end execution.
system -level debug & analysis: gain a strong understanding of chip micro-architecture and features, investigate, debug, and resolve cross-block issues to guarantee feature correctness and compliance
cross-team collaboration: work closely with multiple teams within organizations such as architecture, u-arch, firmware and all units inside the nic
ai-enhanced development: accelerate development by leveraging cutting-edge ai coding tools and frameworks.
Requirements:
what we need to see:
electrical engineering b.sc. or computer engineering b.sc. graduate with high scores or equivalent experience
8+ years of experience in verification or hw simulation
strong debugging, problem solving and analytical skills
innovation mindset - a proactive approach to adopting new methodologies and coding tools to solve complex challenges
a team player with good communication and interpersonal skills
ways to stand out from the crowd:
prior design or verification experience of high-speed interconnects, smart nic and/or SOC
knowledge in network flows and protocols
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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18/03/2026
Location: Yokne`am
Job Type: Full Time
We are looking for a system engineer to join our Failure Analysis engineering team under the System Product Engineering group in the company. As a System Failure Analysis (FA) Engineer, you are responsible for the end-to-end investigation of product failures. You act as the Failure analysis product owner diagnosing complex issues that span Hardware, Software, Firmware, and Mechanical boundaries of the investigation, synthesizing data from all engineering disciplines to reach a definitive root cause. While you provide the architectural oversight for the team, you remain deeply technical and active in the laboratory environment.

What Youll Be Doing:

​Hands-on Lab Investigation: You are active in the lab environment. You perform advanced debugging, characterize system behavior, run reproductions of failures in the lab, and utilize sophisticated lab equipment to validate hypotheses, bridging the gap between high-level data and physical hardware reality.

Multidisciplinary Failure Analysis: Lead deep-dive investigations into system-level failures, understand and analyse customer usage for the product, diagnose how software execution, firmware logic, and hardware components interact to cause specific failure modes.

​Root Cause Ownership: Drive the investigation lifecycle from initial symptom to final physics-of-failure or logic-error identification.

​Task Force Leadership: Orchestrate and lead cross-organizational technical task forces at the company level. You align experts from HW, SW, Mechanical, and NPI teams to solve high-priority technical problems.

​Advanced Data & AI Integration: Define and utilize sophisticated data analysis tools and AI-driven methodologies. You correlate customer failure patterns with production telemetry and RMA history to identify hidden trends and systemic risks.

​Customer Quality Support: Take part in the customer interface by interacting with NVIDIAs Customer Quality Engineers. You provide the deep technical evidence and root-cause clarity needed for quality reports and high-level technical presentations.

​Strategic Lab Direction: Define the high-level debug strategy and complex test plans for the lab. You guide hardware practical engineers on characterization requirements and system-level stress testing.​
דרישות:
What We Need to See:

​​Lab Proficiency: Expert-level experience with lab equipment and the ability to conduct complex characterization on state-of-the-art hardware.

System Engineering Depth: B.Sc/B.Tech in Electrical Engineering, or a related technical field.

​Product Development Experience: 5+ years of experience in Product Development, System-Level Debugging, or Architecture. You must understand how a product is designed and manufactured to effectively analyze its failure.

​Full-Stack Debugging Skills: Proven ability to troubleshoot issues where the hardware, software, and firmware interface. You are comfortable navigating different technical domains to find a root cause.

​Data Fluency: Experience using data analysis tools and a strong interest in applying AI/Machine Learning to automate and scale failure analysis processes.

​Leadership Presence: The ability to lead technical teams through high-pressure investigations and clearly communicate findings to both engineering and quality stakeholders.


Ways to Stand Out from the crowd:

​Hybrid Technical Background: Experience in Board Design combined with SW or Firmware development.

​NPI to Mass Production Expertise: A track record of solving technical problems during the transition from prototype to high-volume manufacturing.

​Data Tooling: Experience building custom Python scripts or SQL dashboards to visualize and analyze global product failure distributions.

​Failure Avoidance Mindset: Ability to provide technical feedback to R&D teams based on FA findings to improve the robustness המשרה מיועדת לנשים ולגברים כאחד.
 
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5 ימים
Location: Yokne`am
Job Type: Full Time
we are hiring a skilled senior dpu performance Validation engineer for our dpu product lines. this includes chip architecture performance characterization, debug, and validation across single-die and multi-die systems. working in the network silicon engineering group, you will be responsible for debugging, analyzing, and validating performance and functional behavior of current and future silicon devices. you will collaborate with chip design, verification, fw, and architecture teams to ensure successful product development with bold product cycles. the qualified candidate should be comfortable working in simulation and emulation environments, with strong skills in rtl-level debug, waveform analysis, and system -level performance root cause analysis.
what you will be doing:
learn and analyze system -level operation of dpus
debug and root-cause performance issues in pre-silicon environments, across rtl, waveform traces, and multi-die system simulations.
collaborate closely with design, verification, architecture, and performance modeling teams to isolate and fix issues.
develop and improve validation methodologies for performance experiments and data collection.
automate repetitive debug and validation tasks to scale coverage and efficiency.
Requirements:
b.sc. in electrical engineering, computer engineering, or equivalent
5+ years of experience in asic development/validation.
strong background in asic debug, including reading rtl, analyzing waveforms, and root-causing functional or performance issues.
hands-on experience with performance validation and analysis at the system level (die-level or multi-die systems).
proficiency with Python and C / C ++ in a Linux environment.
excellent interpersonal skills and ability to work optimally as part of a multi-functional team.
ways to stand out from the crowd:
shown expertise in performance modeling, traffic generation, or architecture studies.
experience with modern interconnects and protocols (e.g., pcie, ethernet, chi).
familiarity with emulation platforms (e.g., palladium, veloce, fpga prototyping).
passion for experimental work, data -driven validation, and creative problem solving.
This position is open to all candidates.
 
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5 ימים
Location: Yokne`am
Job Type: Full Time
looking for senior software program manager that will be responsible for software programs and projects. the pm should drive planning and execution of fw/sw projects while aligning with corporate priorities and constraints.
 a leading supplier of innovative end-to-end infiniband and ethernet connectivity solutions and services for servers and Storage. we offer best-in-class solutions that include adapter cards, switches, cables, and software to support networking technologies. our products optimize data center performance and deliver industry-leading bandwidth and scalability. in addition, we serve a wide range of markets including high-performance computing, enterprise, data centers, cloud computing, Big Data and web 2.0. we are constantly reinventing ourselves to stay ahead of the market and bring groundbreaking products and services to the industry. our product line is focusing on delivering the most optimized ethernet solutions for industries like media and entertainment as well as any other industry that can benefit from our datastream and tcp/ip acceleration. 
what you'll be doing:
you will manage the networking software programs for nvidia next generation ai  data centers 
responsible to coordinate between all project stakeholders such as marketing, engineering teams in il and around the world, operations, etc. from initial requirements definition through architectural stage, execution, and delivery.
develop and execute feature planning and prioritization of perception capabilities to meet the software programs' needs
identify risks, gaps, and bottlenecks in time, and find resolution with technical leaders and project management
work with product managers, architects, and engineers to ensure consistency with company strategy, commitments, and goals
Requirements:
what we need to see:
b.sc. or m.sc. in Computer Science, electrical engineering, or related field
expert with software project management methodologies and tools
8+ years experience in software project management or leadership
experience in software development over hardware/silicon products
teammate, independent, responsible, capable of multi-tasking, ability to drive people and tasks
excellent verbal and written communication skills with english proficiency
ability and willingness to work in a dynamic environment and flexible hours, with teams all over the world 
ways to stand out from the crowd:
technical orientation, including the ability to conduct technical discussions
experience with tools such as ms excel, ms project, power BI
networking background
experience in multiple groups coordination
familiarity with sw agile concept
if you're creative and autonomous, we want to hear from you! nvidia is committed to fostering a diverse work environment and is proud to be an equal opportunity employer. as we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
This position is open to all candidates.
 
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4 ימים
חברה חסויה
Location: Yokne`am
Job Type: Full Time
looking for a Hardware Engineer for our system product engineering group. the candidate will take full responsibility for networking systems product support engineering matters. the position requires an understanding of hardware, firmware/software, mechanical integration, and manufacturing. the candidate will supervise product engineering activities in a various cm (contract manufacturing) lines, working closely with groups across the networking organization: hardware/software/firmware r&d, architecture, TEST engineering, quality & reliability, and operations groups. the candidate will take part in direct communications with nvidia internal and external teams. the position provides an opportunity to gain deep knowledge of nvidia networking systems and a system -level view of our solutions, along with working in a dynamic and positive environment.
what you'll be doing:
leading cross-organizational task forces: you will be responsible for managing and leading cross-functional teams to address quality events and failure modes in nvidia's networking products. this involves coordinating efforts from various departments, such as hardware, software, and manufacturing, to collectively work toward identifying and resolving issues
root cause analysis and TEST planning: you will perform in-depth root cause analysis by meticulously analyzing failure modes monitor and control the TEST yield for all stations
onsite engineering support: you will be the technical owner for all TEST issues, TEST infrastructures, and TEST setup and will have to deliver fast and professional responses for all issues
the workplace is located at the Flex factory in migdal haemek, israel
Requirements:
what we need to see:
b.s. C in electrical engineering, or equivalent experience
5+ years of technical experience in hardware design/ system
experience with failure analysis/debugging/architecture or product engineer
familiar with the manufacturing processes of electrical products
proficient with lab equipment and lab setups and troubleshooting skills
a highly motivated teammate who always stays up-to-date with new technologies and fa methodologies
proficient english is required
ways to stand out from the crowd:
experience as a TEST engineer or system /product engineer
experience in board design/ system
familiar with ict / jtag technology and functional tests
Linux operating systems, and programming languages such as PERL / Python
This position is open to all candidates.
 
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