דרושים » תוכנה » senior dpu performance Validation engineer

We are looking for a Senior networking test engineer with strong system‑level debugging skills to join our End‑to‑End Verification team. You will work on cutting‑edge Ethernet‑based AI clusters, owning complex issues across hardware, system software and AI workloads. We are widely considered to be one of the technology worlds most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!

What youll be doing:

Design and review test and product requirements across the Ethernet / NIC / DPU / Switch portfolio, focusing on large‑scale AI cluster behavior.

Build and maintain realistic customer‑like testbeds, including heterogeneous hardware, OS / driver combinations and complex network fabrics.

Own end‑to‑end cluster troubleshooting: reproduce customer scenarios, triage across the stack and drive issues to root cause and fix.

Read and understand relevant source code to identify defects, validate fixes and improve logging and instrumentation.

Collaborate closely with development teams to debug NCCL, RoCE/RDMA and related networking components using logs, code inspection and targeted experiments.

Define tests and guide the automation team to implement robust suites that produce actionable logs, metrics and traces.

Run Regression, Performance, Functional and Scale testing, analyze results and provide clear, data‑driven reports to stakeholders.

Profile and benchmark deep learning training and inference workloads, correlating model‑level metrics with system and network telemetry to uncover bottlenecks.

We are looking for a Senior networking test engineer with strong system‑level debugging skills to join our End‑to‑End Verification team. You will work on cutting‑edge Ethernet‑based AI clusters, owning complex issues across hardware, system software and AI workloads. NVIDIA is widely considered to be one of the technology worlds most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!

What youll be doing:

Design and review test and product requirements across the Ethernet / NIC / DPU / Switch portfolio, focusing on large‑scale AI cluster behavior.

Build and maintain realistic customer‑like testbeds, including heterogeneous hardware, OS / driver combinations and complex network fabrics.

Own end‑to‑end cluster troubleshooting: reproduce customer scenarios, triage across the stack and drive issues to root cause and fix.

Read and understand relevant source code to identify defects, validate fixes and improve logging and instrumentation.

Collaborate closely with development teams to debug NCCL, RoCE/RDMA and related networking components using logs, code inspection and targeted experiments.

Define tests and guide the automation team to implement robust suites that produce actionable logs, metrics and traces.

Run Regression, Performance, Functional and Scale testing, analyze results and provide clear, data‑driven reports to stakeholders.

Profile and benchmark deep learning training and inference workloads, correlating model‑level metrics with system and network telemetry to uncover bottlenecks.

Join our DOCA Verification team as a Senior Software Verification Engineer and help shape the future of Data Processing Unit (DPU) and network interface cards software. We are seeking a highly motivated and skilled engineer with hands-on technical experience to verify the design and implementation of next-generation software features, with a focus on solving modern hyper scaler advanced networking aspect like congestion control and optimized network usage.

What you'll be doing:

Collaborate with software, architecture, product, and DevOps teams to define test requirements, coordinate releases, and deliver high-quality products.

Take end-to-end ownership of features: develop test plans, implement, and fully automate testing (primarily in Python).

Design, build, and maintain automated test scripts and frameworks.

Validate software functionality and performance through system-level and integration testing in Linux-based and virtualized environments.

Analyze test results, file bugs, track issues to closure, and ensure robust solutions.

Drive continuous improvement in verification flows and contribute to process and methodology enhancements.

Set up, maintain, and optimize test environments using Linux, Docker, and virtual machines.

Monitor nightly regression systems, analyze failures, and provide thorough root-cause analysis across hardware, OS, and software layers.

seeking a highly motivated and hardworking software engineer with hands-on capability technical experience, to verify the design and implementation of the next generation data processing unit software, with wide range of features related to Cyber security and Embedded systems. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting data centers across the world. at nvidia, we're united in our quest to transform the way smart adapters are used.
what you'll be doing:
collaboration & communication: work closely with software, architecture, product and DevOps teams to define TEST requirements, coordinate releases, and ensure high-quality product delivery.
end-to-end feature ownership: deep dive into feature sets, taking responsibility from TEST plan development to final implementation and full automation
develop and automate testing: design, implement, and maintain automated TEST scripts and frameworks (primarily in Python ) to verify the correct functionality of our software products
system & integration validation: validate software functionality and performance through system -level and integration testing, utilizing Linux -based environments and virtualization tools.
defect analysis: analyze TEST results, open bugs and track issues to closure, ensuring robust and scalable solutions.
continuous improvement: drive design verification flows, contribute to methodology improvements, and leverage planning/tracking systems to manage release progress and build release indicators.
TEST environment management: set up, maintain, and optimize TEST environments using Linux, docker, virtual machines, and other modern tools.
regression monitoring: operate, monitor, and analyze failures in the nightly regression system, providing methodical root-cause analysis across hardware, os, and software layers.

we're looking for a hardware architect for our nic and dpu division. in this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of nvidias next generation nic and dpu products. your role will be cross-disciplinary, working with software, asic design, verification, physical design and platform teams to improve performance and debug.
what you'll be doing:
learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and Verification engineers.
define the implementation of the most sophisticated debug features of our next products, balancing architecture requirements with backend, execution, and design considerations.
define the implementation of debug capabilities to support performance validation and improvements
understand our system debug requirements and help define the por of our nic and dpu product line.
face the most challenging full-chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.
work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.
thoroughly understand SOC flows, pcie, ethernet, infiniband and nvlink protocols.

we are looking for a senior networking TEST engineer with strong systemlevel debugging skills to join our endtoend verification team. you will work on cuttingedge ethernetbased ai clusters, owning complex issues across hardware, system software and ai workloads. widely considered to be one of the technology worlds most desirable employers. we have some of the most forward-thinking and hardworking people in the world working for us. if you're creative and autonomous, we want to hear from you! 
what youll be doing:
design and review TEST and product requirements across the ethernet / nic / dpu / switch portfolio, focusing on largescale ai cluster behavior
build and maintain realistic customerlike testbeds, including heterogeneous hardware, os / driver combinations and complex network fabrics
own endtoend cluster troubleshooting: reproduce customer scenarios, triage across the stack and drive issues to root cause and fix
read and understand relevant source code to identify defects, validate fixes and improve logging and instrumentation
collaborate closely with development teams to debug nccl, roce/rdma and related networking components using logs, code inspection and targeted experiments
define tests and guide the automation team to implement robust suites that produce actionable logs, metrics and traces
run regression, performance, functional and scale testing, analyze results and provide clear, datadriven reports to stakeholders
profile and benchmark deep learning training and inference workloads, correlating modellevel metrics with system and network telemetry to uncover bottlenecks

in this role, you will help build and evolve systems that support performance analysis, telemetry, and optimization for large-scale gpu- and cpu-based clusters used in ai and high-performance computing environments. you will work closely with hardware, networking, firmware, and software teams to collect, analyze, and interpret performance data from live systems. this is a fast-paced r&d environment where system behavior and requirements evolve rapidly, requiring adaptable engineering solutions and strong analytical thinking.
what youll be doing:
profile, benchmark, and analyze ai and hpc workloads on gpu and cpu clusters
explore performance characteristics of high-performance networking and collective communications (e.g., nccl, rdma, mpi, roce)
identify performance bottlenecks across networking, compute, memory, and system architecture
develop and enhance performance analysis, benchmarking, and diagnostic tools
define performance TEST plans and establish expectations for new technologies and platforms
collaborate across hardware, firmware, networking, systems, and software teams to provide actionable performance insights
support telemetry collection and data refinement efforts to enable accurate performance analysis
maintain high standards for  data quality, reproducibility, and traceability of performance results

we are looking for best-in-class senior full-chip Verification engineer to join our networking silicon team. in this role, you will be responsible for the development and verification of our next-generation nics at the system level. you will contribute to the architecture of high-speed communication devices by driving full-chip verification execution for the networking solutions powering the worlds most advanced data centers, enjoy working in a meaningful, growing environment where you make a huge impact in a technology-focused company.
what youll be doing:
full-chip verification & execution: own complex system -level features by defining verification plans and driving the end-to-end execution.
system -level debug & analysis: gain a strong understanding of chip micro-architecture and features, investigate, debug, and resolve cross-block issues to guarantee feature correctness and compliance
cross-team collaboration: work closely with multiple teams within organizations such as architecture, u-arch, firmware and all units inside the nic
ai-enhanced development: accelerate development by leveraging cutting-edge ai coding tools and frameworks.

this senior role places you at the center of innovation, where you will have a direct impact on our business and technology by solving sophisticated technical challenges. its a unique opportunity to shape our technology and empower customers to build the supercomputers and ai fabrics of tomorrow.
what you'll be doing: lead the architectural design, development, and optimization of cutting-edge pcie firmware, using ai-driven modeling and insights to deliver exceptional performance.
serve as a trusted technical expert by investigating, debugging, and resolving challenging pcie firmware issues for our most important customers.
collaborate closely with our chip design, verification, software, and Architecture Engineers to find root causes and develop robust, long-term solutions.
champion the integration of ai-assisted diagnostics and generative ai tools across the entire development lifecycle to boost team productivity and innovation.
translate customer needs and field data into actionable feedback that directly shapes the future of our products.

we seek a V&V Engineer with a strong background in validation to join the interconnect validation team. this position will be part of the product engineering team that crafts and integrates software tests for our company networking products into the production lines. you will handle various projects across teams, complete new lab setups, review the hw design, build validation plans, implement automated tests, perform manual scenarios, and report bugs. are you passionate about attention to detail and taking ownership of end-to-end validation for our interconnect products? join our team and bring your expertise to life!
what you'll be doing:
collaborate with multi-functional teams across engineering, software development, and hw to identify TEST requirements
define and build setup topologies for appropriate product coverage
build a validation plan, complete, and integrate tests for the new interconnect products to address the business needs
debug sw & hw failures during the validation and take action to address it
report bugs found during validation, assist with reproduction, and debug to understand the root cause, and follow up to close it
deploy the product validation into the nightly automation tests and track during the daily meeting