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As a Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers AWS at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.

Required Software Post Silicon Validation Lead
Job Description
Meet The Team
Welcome to the Post-Silicon Validation Team at Silicon One , where startup energy meets the scale of a global technology leader.
As part of Silicon One Group, we help deliver the silicon, optics, and hardware platforms behind our core Switching, Routing, and Wireless products used by enterprises, service providers, public sector, and non-profit organizations worldwide.
Our team works side by side with verification engineers, designers, and cross-functional partners to validate complex ASICs across their full lifecycle and ensure outstanding product quality.
At the center of this innovation is Silicon One, the industrys only unified silicon architecture, powering platforms from Top-of-Rack switches to web-scale data centers and critical AI infrastructure.
Your Impact
Lead validation work for complex networking ASICs, from first silicon bring-up to production.
Manage and support a small validation team, and guide daily technical work.
Own the validation plan for features, performance, power, and reliability.
Find and solve issues across silicon, firmware, drivers, and system software.
Work with architecture, SDK, and firmware teams to improve product quality, stability, and test coverage.
KEY RESPONSIBILITIES:
Lead post-silicon validation and debug for networking ASIC projects.
Manage tasks and technical direction for a small validation team.
Build and run validation plans for function, performance, power, and reliability.
Drive silicon bring-up, stepping checks, and production readiness.
Develop validation tools and automation using C/C++ and Python.
Run stress and long tests to find hidden silicon problems.
Debug hardware and software issues in the lab.
Validate networking features and interfaces (for example Ethernet, PCIe, SerDes, DDR, SPI, I2C, UART).
Add tests to regression flows and track progress until closure.
Document results, issues, and recommended fixes clearly.

Required PHY System Technical Leader
Job Description
Join the PHY system team at Silicon One, a pivotal part of our silicon development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
Key responsibilities include:
Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.
What Youll Do:
Youll be part of the group driving next-generation network devices-Silicon One-within a startup-like atmosphere inside a well-established, leading corporation.
Our unique design center integrates all silicon hardware and software development disciplines under one roof. We are revolutionizing the industry by building a new internet for the 5G era, with a unified, programmable silicon architecture that will underpin our future routing products. Our devices are designed for adaptability across service providers and web-scale markets, delivering high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.

In this role you will develop system level software, targeting chip architecture, functional correctness and performance, running on various platforms and validating chip functionality.

We're looking for exceptional engineers to join our Pre-Silicon Verification team - the team that sits at the very center of the chip development lifecycle. Verification in our company isn't a downstream checkpoint - it's the connective tissue that spans the entire product journey:
It starts at product definition - we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written
It extends into software - we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack
It reaches into physical design - we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality
It closes the loop - from spec to silicon, our verification touches every team and every stage of chip development
What sets us apart:
Agentic AI is embedded in our workflow - not as an experiment, but as a core part of how we design and verify chips.
Cutting-edge methodologies drive every stage of our verification process
Relentless innovation - we don't settle; we actively seek new approaches that raise the bar on silicon quality.
We do classic functional verification(SV/UVM/TLM), but beyond that, we touch physical design aspects, to ensure that the quality of our silicon is beyond logical functionality.
Performance optimization at all levels it is at the heart of our targets on top of logical correctness verification.
If you want to be at the nerve center of chip development - where your work connects every discipline and powers the backbone of AWS Graviton - this is your team.

Required ASIC Design Engineering Technical Leader
Job Description
Meet the Team
Join the Silicon One Front-End Design team, at the core of our silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
Silicon One is transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

In this highly-visible role you will assume responsibility over a full range of DFT in an extremely challenging project, leading a talented team of engineers, working closely with frontend and backend teams. You will participate in architecture and design reviews, create design solutions for testability, debug ability, reliability and yield improvement. You will provide design constraints for implementation and sign-off. You will build work plans, drive and track their execution. You will be closely involved in silicon bring-up, reliability testing and advanced physical failure analysis activities, and will be responsible for getting a high-quality product out into AWS fleet for millions of our customers quickly. Come and join us as we work hard, have fun, and make history.

We are looking for a motivated Hardware Engineer to join our Hardware team in Raanana.

You will have the chance to develop your own skills in a flexible and energetic work atmosphere with friendly and experienced colleagues. You will have helpful supervision, opportunity to learn, modern tools and flexible work culture.

If you want to be a part of our growing company that is driven by innovation and is focused on building a future together with our employees, consider applying.

Principle duties and responsibilities:

Design hardware modules, subsystems and systems for synchronization products.

Develop schematics and guide PCB layout (high-speed, mixed-signal, power).

Select and evaluate components (ICs, power devices, oscillators, interfaces).

Design high-speed interfaces (e.g., 10G/25G Ethernet) with signal integrity considerations.

Contribute to hardware design specifications (HDS) and documentation.

Support system-level integration (HW, FPGA, SW).

Define and execute validation and integration test plans.

Debug complex board and system-level issues (mixed-signal, high-speed).

Perform lab bring-up, measurements, and performance characterization.

Support product transfer to manufacturing (NPI).

Collaborate with manufacturing and test teams for production readiness.

Investigate and resolve issues during production and field operation.

Ensure product reliability, quality, and compliance with applicable standards.

Functional Collaboration.

Work closely with FPGA, software, system, SIT/SVT and mechanical teams.

Participate in design reviews and technical discussions.

Interface with suppliers and external partners as required.

Evaluate and introduce new technologies and components.

Drive improvements in performance, power efficiency, and cost.

Contribute to system architecture discussions and design trade-offs.

Required ASIC Design & Verification Engineer
Job Description
Meet the Team
Join the Silicon One Front-End Design team, at the core of our silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
Silicon One is transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact:
Review micro-architecture specifications
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab.

Required PHY Post Silicon Validation Engineer
Job Description
What You'll Do
Youll be joining the post silicon validation team in PHY system group at Silicon One group as part of the silicon development.
Our team deals with PHY and system aspects of the SerDes communication IP: PHY FW, calibrations, system definitions and operations and post-silicon validation including developing the automation infrastructure and tools.
We use latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.
Who You'll Work With
You'll be part of our Group driving our game changing next generation network devices - Silicon One. Our unique team works in a startup atmosphere inside a stable and leading corporation. The position includes hands on work in our lab in Caesarea and Netanya.
Our design center is unique - hosting all silicon HW and SW development disciplines inside one site.
We are transforming the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all our future routing products.
Our devices are designed to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.
Silicon One is a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine!

We are seeking talented, creative and disciplined engineers to join the best-in-class team that plays a significant part in the development of new silicon for our eco-systems by engaging in a dynamic, highly collaborative environment. As a Wireless MAC System Architect, you will be a core member of our highly innovative and visible Wireless System-on-Chip (SoC) design team that defines modem architectures, develops MAC-layer algorithms, and invents embedded DSP algorithms for chips enabling exciting new wireless applications. You will be responsible for developing state-of-the-art wireless SoC products that are enjoyed by millions of our customers. Application areas include ultra-wideband sensing and specialized wireless audio; products enabled or improved by our teams SoCs include specialized audio headsets (such as AirPods), watches and iPhones.

In this role you will be responsible for the architecture of the Connectivity IP with focus on the MAC sub-system: - Define, document and Spec Connectivity MAC architecture and performance requirements.
- Analyze & simulate the performance of the Connectivity IP in real-life use-cases, achieving benchmarking performances in several metrics, including Throughput, Robustness, Co-existence with other Wireless IPs and more.
- Working closely with other architects (PHY, Power Management, FW and SW) to introduce best in class Connectivity IP solution.
- Develop innovative system architectures and protocols to deliver best-in-class performance for the MAC subsystem of custom wireless silicon solutions.
- Introduce cross-domain features where opportunities exist for innovation to achieve enhanced performance.
- Produce MAC architecture, specifications and corresponding performance/reference modeling in support of digital HW and FW design and verification efforts.
- Develop and maintain a MAC systems infrastructure applying the best methodologies for system-level simulation, pre-silicon prototyping (including emulation and FPGA prototyping), FW QA, regression and MTBF testing, and system verification to ensure first-time design success.
- Support the delivery of new wireless technologies to the Product Systems teams.

Required PHY System
Job Description
Join the PHY system team at Silicon One, a pivotal part of our silicon development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
Key responsibilities include:
Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.
What Youll Do:
Youll be part of the group driving next-generation network devices-Silicon One-within a startup-like atmosphere inside a well-established, leading corporation.
Our unique design center integrates all silicon hardware and software development disciplines under one roof. We are revolutionizing the industry by building a new internet for the 5G era, with a unified, programmable silicon architecture that will underpin our future routing products. Our devices are designed for adaptability across service providers and web-scale markets, delivering high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.

We are seeking a CAD LEQ (Logical Equivalence Checking) Engineer to develop, deploy, and support equivalence checking methodologies across complex SoC programs. This role focuses on ensuring functional correctness between RTL, synthesized netlists, and post-implementation designs, while driving scalable, robust sign-off flows.

Responsibilities
Own and maintain LEQ sign-off methodology across RTL-to-GDS flows.
Develop and support flows using tools such as Cadence Conformal and equivalent industry solutions.
Drive power-aware equivalence checking including CPX flows.
Enable ECO flows, ensuring safe and correct implementation of late-stage design changes.
Debug equivalence failures and perform root-cause analysis across RTL, synthesis, and PnR stages.
Collaborate with design, synthesis, PD, and power teams to resolve mismatches and improve convergence.
Optimize runtime, capacity, and scalability of LEQ flows for large SoCs.
Define best practices, guidelines, and automation for LEQ usage across projects.
Partner with EDA vendors to resolve tool issues and drive feature improvements.

Required Senior Electrical Post Silicon Validation- Silicon One
Job Description
Meet the Team
We are a dynamic group of engineers dedicated to pushing the boundaries of technology. Our mission is to validate and drive the performance of Silicon One products, ensuring they meet the highest standards of quality and reliability.
Operating at the forefront of technology, we work with latest, high-speed, and power-hungry devices. Our small, but highly influential team thrives in this challenging environment, applying our expertise to impact the future of networking technology. With a commitment to excellence and a passion transformative technology, we are shaping the future of high-performance Networking and delivering unparalleled value in every project we undertake. Join us, and be a part of a team where professionalism meets impact!
Your Impact
Drive the resolution of complex silicon performance and characterization issues through deep, multi-functional collaboration with architecture, design, and software teams. Leverage these technical insights to provide critical feedback that directly influences the design, debuggability, and architectural specifications of future silicon components
Key Responsibilities:
Lead the Electrical Post Silicon Validation efforts for Silicon One products, focusing on high-speed and power-intensive devices. Collaborate with multi-functional teams to drive the silicon validation process, from architecture through to physical design and DFT. Analyze and interpret characterization data to guide design improvements and ensure product excellence. Develop and execute test plans to validate silicon performance and reliability against stringent specifications. Troubleshoot and resolve issues related to silicon performance and characterization.
Why Join Us:
Be part of team at the forefront of silicon technology, working on the most advanced products in the market. Work closely with some of the best engineers in the industry, driving innovation and excellence in silicon characterization. We are a fast growing team that values talent and provides ample opportunities for professional development and career advancement.

Develop and maintain internal EDA tools and frameworks for RTL assembly and connectivity checking.
Implement efficient algorithms for hierarchical RTL construction, module binding, and interface consistency across complex SoCs.
Build intelligent connectivity, visualization, and debug utilities.
Collaborate with front-end design, DFT, and integration teams to align methodologies and define tool requirements.
Drive automation and performance improvements, including runtime optimization and scalability across large designs.
Support adoption, documentation, and user training for internal design teams.