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We're seeking a passionate and skilled Embedded Firmware Engineer to play a pivotal role in delivering the next generation of us. In this highly visible position, you'll be at the intersection of hardware and software, collaborating closely with logic designers to deeply understand system-level operations and performance requirements for hardware validation. In this role, you will develop critical low-level embedded firmware specifically designed to validate hardware functionality, ensure conformance, and drive performance during the bring-up and testing phases of new silicon. This involves designing, developing, and integrating complex drivers, diagnostic tests, and infrastructure essential for SoC bring-up, post-silicon validation, and debugging activities. Ultimately, you'll lead hands-on firmware development, system-level validation, and problem-solving at the hardware-software interface in a dynamic, collaborative environment, with your work directly enabling the successful launch of future products by ensuring our silicon meets the highest standards.

As member of the DV CAD team, you have the opportunity to impact our engineers who develop next generation of our products!
You will be responsible for developing software solutions used by thousands of DV engineers globally. You will be supporting design process of all chip families we make (iPhone, iPad, Mac, our Watch and more), and your work will help streamline this complex process. This role combines DV knowledge alongside modern software engineering practices. Your work will be very diverse, and you will have broad impact contributing to the success of us.


You will develop and drive software development of multiple tools across the DV space, including cloud-native services, GUI, LLM harness, CI/CD. Your work will span from software development and architecture to collaborating with DV engineers, working with EDA vendors, and supporting critical project milestones.

Responsibilities
Developing and maintaining LLM harness for agentic DV workflows, and being responsible for benchmarking and improving accuracy of agentic workflows.
Building and managing cloud-native services running on k8s, including CI/CD, containerization, alerting, databases, GUI and monitoring.
Communication with DV stakeholders and working to understand user requirements.
Writing and maintaining Python scripts used as part of design simulation flows.
Supporting multiple projects simultaneously.

The AI VLSI department develops top notch NPU that enables the execution of state-of-the-art LLMs, Generative AI models, and neural networks with exceptional performance, impacting multiple hardware and software teams across the company facing amazing PPAA challenges of the edge market.
In this role, as VLSI Team Leader in the AI VLSI department, you will lead a team of engineers developing cutting edge VLSI products such as - DSP, HW accelerators and AI Processors for the edge market, with full responsibility on the Front-End Design.
You will drive the development of robust, scalable, and efficient VLSI design, working closely with global Architecture, hardware simulator and Software teams to shape our companys next generation of AI solutions.
We are looking for an exceptional hands-on leader with strong technical expertise, proven experience leading VLSI Front-End Design engineers, and a track record of delivering complex, state-of-the-art products on time and in production ready quality.
The ideal candidate is execution-driven, innovative, and passionate about building high-performing team and cutting-edge AI technology.
Responsibilities
Manage and lead a team of Front-End Design engineers.
Be accountable for the teams development lifecycle, including architecture, development, validation, and release, focusing on meeting PPAA targets.
Lead development of advanced VLSI IPs for AI processors, DSP and HW accelerators while continuing pushing the VLSI design methodologies, procedures, sign off and AI tools assimilation to its next level.
Support system bring-up, debugging, and customer-facing activities when needed.

In this role, you will have a direct impact on our product quality. As a team member in our SW team, you will be responsible for the development and operating of different SW and HW blocks in our system, analyze, optimize and debug your work and test the results and explore issues on your developed modules and other modules you will integrate with.
You will solve complicated failures and bugs and will dive into the code and the HW to understand why the failure occurs. You will be responsible for managing your developed products, including full test plan that will drive our system to zero bugs on the customer side
You will use the newest AI tools to speed up your development and debugging
Responsibilities:
Design, implement, maintain, optimize, and run various SW parts that are needed for the 5G Modem, including HW blocks drivers programming and operation.
Analyze and debug test results and explore results and issues.
Verify functionality and code performance of your developed code.
Track problematic code parts and work on improving them, WRT code cycle performance and code size performance.

As part of the Group, we combine the agility and specialized expertise of a focused medical imaging company with the capabilities of a global technology organization. Our activity spans advanced system development, manufacturing, integration, testing, and support of digital imaging solutions for customers around the world.

We are looking for a CAD/Emulation Engineer to join our infrastructure team. This position is providing hands-on experience with advanced VLSI CAD/Emulation flows and infrastructure.
Key Responsibilities
Develop and maintain automation scripts for front-end Emulation and VLSI CAD flows and automation.
Support execution and releases of VLSI artifacts while maintaining advanced CAD flows.
Assist in improving infrastructure efficiency and tool integration.
Work with advanced version control systems and CI/CD pipelines for regression and build environments
Responsible for top notch emulation methodologies and procedures.

Lead a team of compiler engineers responsible for our company's open source based toolchain and graph compiler. You will be a hands-on team leader - driving architecture decisions, guiding engineers, and delivering compiler capabilities across all our company hardware targets. Our team embraces an AI-agentic development flow, leveraging AI coding agents to accelerate engineering productivity, and we are looking for a leader who champions this approach.
Responsibilities
Lead development of our company's open source based toolchain targeting custom DSP and NPU architectures. Drive design and delivery of graph compilation flows: transformations, operator mapping, and code generation. Champion AI-agentic development practices within the team - integrating AI coding agents into day-to-day engineering workflows. Mentor engineers and conduct code reviews; build a high-quality engineering culture. Collaborate with hardware architecture, algorithms, and software teams globally. Own team planning, prioritization, and on-time delivery of toolchain features. Contribute hands-on to design, implementation, and performance tuning in C++ and Python.

The System team defines and develops cutting-edge 5G technology. In this role, you will lead the system team responsible for defining our next-generation modem products and developing modem algorithms, working at the intersection of research, system design, and implementation.
Responsibilities
Lead a team of senior system and algorithm engineers responsible for developing innovative 5G modems.
Partner closely with VLSI and SW teams implementing the modem HW and SW and align on system definitions with implementation constraints.
Develop and maintain deep expertise in cellular standards and their implications for modem design.
Lead system and algorithmic research, balancing trade-offs between DSP/SW/HW implementations, performance, implementation cost, real-time constraints, and time-to-market.
Own system definitions, requirements, and implementation from initial research through simulation to official release, including MATLAB/C/C++/SystemC modeling and specification documentation.
Mentor and grow team members, fostering technical excellence and professional development.

Required Staff RTL IP/Component Design Engineer, Cloud
About the job
In this role, you will contribute in all phases of complex application-specific integrated circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our latforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Define the block level design document such as interface protocol, block diagram, transaction flow and pipeline, etc.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, and VHDL), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Support synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Required Senior DDR Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing. You will verify digital designs, collaborate closely with colleagues on projects, and perform direct validation. You will construct testbenches that exercise hardware through corner-cases and expose bugs. You will manage the full life-cycle from planning and execution to closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Required Physical Design Engineer, SoC Static Timing Analysis
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. In this role, you will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering exceptional performance, efficiency, and integration.
Responsibilities
Drive the sign-off timing convergence for high-performance designs.
Set up the timing constraints, define the overall static timing analysis (STA) methodology, set up the STA infrastructure and sign-off convergence flows, and work closely with block owners throughout the project for sign-off timing convergence.
Work with logic designers to drive architectural feasibility studies, develop timing, and explore RTL/design trade-offs for physical design closure.