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Job Description
Responsible for the design, development, implementation, and maintenance of automated TEST systems and equipment for company products, from the development stage through production.
Key Responsibilities
* Design and development of TEST systems according to product requirements:
* Define projects, including design approval, budget, and timelines.
* Develop automated tests, hardware, and software, and perform troubleshooting.
* Responsible for documentation, technical instructions, SOW, ATP, and related documents.
* Full responsibility for replication of existing TEST equipment, including procurement, assembly, integration, and testing.
* Provide Technical Support and troubleshooting for production lines and at subcontractors.
* Participate in Design for Testability (DFT) activities throughout the product development process.

Reports to:
ATE team leader

The Senior Silicon Photonics PIC Design Engineer will help build next-generation Photonic Integrated Circuits (PICs) that power high-performance optical interconnect solutions. In this role, you will lead the design, simulation, layout, and system-level testing of advanced silicon photonics components, while contributing to optical test instrumentation for emerging semiconductor test markets.
As a member of the Silicon Photonics Engineering Staff, you will be a key player in the definition, implementation, and validation of complex automated test equipment that interfaces optical ports of silicon photonic devices at all stages of fabrication, from wafer probe to packaged test.
Lead the design, simulation, layout, and system-level testing of advanced silicon photonics components and Photonic Integrated Circuits.
Utilize simulation and design tools, including Ansys/Lumerical and Cadence Virtuoso, to design, validate, and optimize photonic designs.
Collaborate closely with design, layout, EIC, packaging, validation, quality, and system architecture teams to develop high-performance integrated photonic circuits and validate link performance.
Partner with fab and process engineers to define and optimize device design and implement process monitoring structures.
Develop test and qualification plans in coordination with validation and quality engineering teams.
Conduct rigorous testing and characterization of devices and PICs, including passive and active photonic components.
Engage in direct collaboration with silicon foundries to streamline processes and support successful tape-out execution.

The Senior Silicon Photonics PIC Design Engineer will help build next-generation Photonic Integrated Circuits (PICs) that power high-performance optical interconnect solutions. In this role, you will lead the design, simulation, layout, and system-level testing of advanced silicon photonics components, while contributing to optical test instrumentation for emerging semiconductor test markets.
As a member of the Silicon Photonics Engineering Staff, you will be a key player in the definition, implementation, and validation of complex automated test equipment that interfaces optical ports of silicon photonic devices at all stages of fabrication, from wafer probe to packaged test.
Lead the design, simulation, layout, and system-level testing of advanced silicon photonics components and Photonic Integrated Circuits.
Utilize simulation and design tools, including Ansys/Lumerical and Cadence Virtuoso, to design, validate, and optimize photonic designs.
Collaborate closely with design, layout, EIC, packaging, validation, quality, and system architecture teams to develop high-performance integrated photonic circuits and validate link performance.
Partner with fab and process engineers to define and optimize device design and implement process monitoring structures.
Develop test and qualification plans in coordination with validation and quality engineering teams.
Conduct rigorous testing and characterization of devices and PICs, including passive and active photonic components.
Engage in direct collaboration with silicon foundries to streamline processes and support successful tape-out execution.

As an R&D Mechanical Engineer at Augury, you will own the design of new parts and assemblies, design parts for machining and injection molding, perform analytical calculations and V&V tests.

Youll work closely with mechanical, hardware, V&V, sustain, manufacturing, and external sub contractors, to deliver innovative, reliable, and scalable IoT devices.

A Day In Your Life
Design mechanical parts and mechanisms, for highly challenging environments, from initial concepts, through all design phases, until transfer to production.
Master 3D CAD models and drawings for mechanical components, assemblies, jigs, and fixtures (including release management and GD&T).
Design for plastics: mostly parts for injection molding, compression and other classical manufacturing methods.
Run prototype validation: mechanical inspection, stress testing, sealing, field testing and support high level system validation procedures.
Cooperate with multidisciplinary teams (HW, V&V, FW, Algo), utilizing analytical thinking and strong theoretical background.
Transfer parts for production, in collaboration with the engineering team, and following product lifecycle methodologies.
Work with subcontractors and vendors in Israel and internationally.

Were looking for a talented Game Developer to join our studio in Haifa - a gamer at heart who combines strong technical skills with a genuine understanding of what makes games fun, satisfying, and engaging. The ideal candidate can take a game from an early concept or prototype to a polished, production-ready experience, thinking beyond implementation to gameplay, pacing, feedback, animation, UX, and game feel.

Our main focus is HTML5 game development, with games distributed across multiple web and gaming platforms.





Responsibilities
Build and iterate on core gameplay mechanics, game systems, UI, and player interactions, with a strong focus on game feel and responsiveness.
Bridge art and code by implementing animations, visual effects, transitions, and other technical-art elements that bring the game experience to life.
Work closely with artists to integrate and optimize visual assets while maintaining high visual quality and performance.
Rapidly prototype and iterate on gameplay and visual ideas, turning creative concepts into polished, production-ready experiences.
Take ownership of features and game systems, including debugging, performance optimization, and cross-platform compatibility.
Collaborate with game designers, artists, and product managers, while contributing to reusable tools and systems across the studio.
Contribute to technical decisions, development practices, reusable systems, and tools across the studio.

You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

As the Physical Design Manager, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

Review micro-architecture specifications

Supervise verification team members and provide professional guidance

Implement Verification environment UVM based

Collaborate with Design engineers to resolve bugs and achieve coverage closure

Work with the firmware/Lab teams to verify chip flows

Perform debug, root-cause analysis, and post-silicon validation in the lab

Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the Cisco SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.

Your Impact
Lead and drive DFT verification activities within the Cisco SiliconOne DFT team.

Develop verification plans, environments, checkers, assertions, and coverage models for DFT features.

Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams.

Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features.

Debug complex pre-silicon issues across RTL, verification environments, and DFT logic.

Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV.

Help bridge between general DV methodologies and DFT-specific design and verification needs.

As a Project Manager, you will support multiple ASIC development programs by coordinating execution, tracking deliverables, and enabling collaboration across engineering teams. You will strengthen operational excellence through AI-based automation and tracking solutions. Your work will help teams identify risks and dependencies early, maintain alignment, and deliver programs successfully.

Support Program Managers throughout each phase of ASIC program execution.
Track milestones, action items, dependencies, risks, deliverables, status reports, dashboards, and execution metrics across multiple projects.
Coordinate activities among ASIC, Software, and Business Operations teams, including global stakeholders.
Drive follow-up and accountability to ensure project actions are completed on time.
Develop AI-powered tracking tools and automation solutions that improve project visibility, streamline processes, and strengthen program management methodologies.
Collaborate with engineering and operations teams to maintain alignment and support successful program delivery.

We are excited to announce that the Cisco Silicon One team is undergoing rapid growth, and we are looking for a Senior C++ Software Developer.

Your Impact

Craft and develop software driving the world's most complex infrastructures
Gain intimate knowledge of world-class silicon and programming models
Work with architecture and design teams to define the next generation of ASIC products being developed

In this role, you will contribute to the development of complex ASIC package designs from early planning and exploration through implementation and tapeout. You will collaborate across package design, layout, SI/PI, and silicon teams to help deliver high‑speed, robust, and manufacturable package solutions.

You will participate in package architecture activities, design tradeoff discussions, and technical problem solving while growing your expertise in advanced packaging technologies and system-level integration. This role provides an opportunity to work on some of the most advanced networking silicon products in the industry within a highly collaborative engineering environment.

Responsibilities:
As a member of the Package Design team, you will:

Lead the package design activities including planning, floorplanning, pinout optimization, stack‑up definition, and high‑speed routing support.

Collaborate with SI/PI, silicon floorplanning, layout, and manufacturing teams to ensure high‑quality package solutions.

Support package implementation activities and work closely with layout designers to ensure alignment between design intent and physical implementation.

Participate in technical investigations, design reviews, and tradeoff discussions involving performance, manufacturability, and schedule considerations.

Assist in developing and improving package design methodologies, flows, and best practices.

Contribute to debugging, issue resolution, and package bring‑up activities as needed.

As a Software Engineering Technical Leader, you will drive the technical vision and execution for complex security policy and access solutions that safeguard enterprise networks globally. You will leverage your deep expertise in systems programming using C, C++, and Java to architect and develop robust, scalable software. By providing technical leadership, you will mentor peers, guide architectural decisions, and foster a culture of innovation and continuous improvement within the team. Your work will directly contribute to Cisco's mission by ensuring our network access solutions are secure, programmable, and highly reliable. You will also champion software programmability and integrate automation and orchestration practices to streamline development and enhance product performance, ultimately empowering our customers to connect with confidence.

Lead hands-on lab debugging to fix complex silicon performance, characterization, and yield issues. Use bench findings and board-probing data to give feedback directly to the architecture and design teams. Lead ASIC bring-up on validation boards, focusing heavily on SerDes, high-speed interfaces, and power/clock domains. Run characterization across PVT (Process, Voltage, Temperature) conditions and analyse large datasets to resolve performance bottlenecks and improve chip yield. Write and optimize clean Python code to automate lab equipment and test internal chip logic. Serve as the technical lead for complex hardware debug, defining validation methodologies, and advanced lab measurement techniques for the team.