דרושים » הנדסה » V&V Engineer

We are seeking a highly motivated V&V Automation Engineer to design, develop, and maintain automated test solutions for our cutting-edge medical imaging products. This role involves ensuring the quality and reliability of our software and systems through robust and efficient automated validation and verification processes.
Job Responsibilities
Design, develop, and implement automated test scripts and frameworks for complex medical devices and software applications.
Collaborate with development, V&V, and product teams to understand system requirements, design specifications, and test cases.
Perform comprehensive verification and validation activities, including functional, performance, security, and regression testing.
Analyze test results, identify defects, and work closely with development teams to ensure timely resolution.
Maintain and enhance existing automation infrastructure, tools, and processes to improve efficiency and coverage.
Develop and execute test plans, test cases, and test procedures in accordance with regulatory standards (e.g., ISO 13485, FDA 21 CFR Part 820).
Document test activities, results, and defects accurately and thoroughly.
Participate in design reviews and provide feedback on testability and automation potential.
Stay up-to-date with industry best practices in test automation, software development, and medical device regulations.

As a Senior/Staff Design Verification Engineer, you will be a key architect of quality in our Israel R&D center. You won't just run tests-you will design comprehensive verification strategies for high-performance digital blocks, IPs, subsystems, and full-chip integration. You will work at the cutting edge of AI infrastructure connectivity where "good enough" isn't an option, owning end-to-end verification plans for our most challenging designs. If you thrive on solving complex verification challenges and want to ensure the quality of chips powering the world's largest AI clusters, this is your opportunity.

Key Responsibilities

Verification Environment Architecture & Development

Design and develop comprehensive ASIC verification environments across all levels-from unit-level and subsystems to full-chip integration
Build sophisticated SystemVerilog/UVM-based testbenches including protocol/traffic generators, monitors, checkers, and functional coverage models
Own end-to-end verification plans for highly complex digital blocks, defining the "how" and "what" to ensure 100% functional coverage
Quality Assurance & Debug Excellence

Drive the debug process and leverage advanced methodologies to find critical bugs before silicon
Develop and execute comprehensive test plans to verify functionality, performance, and corner cases
Ensure verification closure through rigorous coverage analysis and assertion-based verification
Cross-Functional Collaboration & Technical Leadership

Partner with design and system architects to solve intricate hardware verification challenges
Work alongside world-class teams where knowledge sharing and technical excellence are the standard
Contribute to verification methodology improvements and automation initiatives

Required Senior Manager PET V&V
Job Description Summary
The PET V&V Manager will lead and oversee all Verification and Validation activities for Positron Emission Tomography (PET) systems and components, ensuring product quality, regulatory compliance, and successful product launches within
Job Description
Job Responsibilities:
* Lead and manage a group of 30-40 V&V engineers and technicians, including team leads, with responsibility for hiring, training, performance management, and career development.
* Develop, implement, and maintain comprehensive V&V strategies, plans, and protocols for PET systems, subsystems, and software, adhering to our quality systems and regulatory requirements (e.g., FDA, CE).
* Oversee the execution of V&V activities, including test case development, test execution, defect management, and results analysis, ensuring thorough coverage and traceability to requirements.
* Collaborate closely with R&D, System Engineering, Quality Assurance, Regulatory Affairs, and Project Management teams throughout the product development lifecycle to define requirements, design testability, and ensure V&V deliverables are met on time and within budget.
* Drive continuous improvement in V&V processes, tools, and methodologies, incorporating industry best practices and lessons learned.
* Review and approve V&V documentation, including test plans, reports, and traceability matrices, ensuring accuracy and completeness.
* Participate in design reviews, risk assessments, and post-market surveillance activities to identify potential V&V implications.
* Represent the V&V team in internal and external audits, providing evidence of compliance and addressing any findings.
* Stay abreast of new technologies, industry standards, and regulatory changes relevant to PET imaging and V&V.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
in this role, you will work as part of a research and development team. you will build verification components, constrained-random testing, and system testing, and drive verification closure. you will verify digital designs, collaborate closely with design and Verification engineers on projects, and perform direct verification. you will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. you will manage the full life-cycle of verification, which can range from verification planning and TEST execution to collecting and closing coverage.the ai and infrastructure team is redefining whats possible. we empower our customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include, cloud customers, and billions of our users worldwide. we're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for cloud, global networking, data center operations, systems research, and much more.
responsibilities
plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
create and enhance constrained-random verification environments using systemverilog and uvm, or formally verify designs with systemverilog assertions (sva) and industry leading formal tools.
identify and write all types of coverage measures for corner-cases.
debug tests with design engineers to deliver functionally correct design blocks.
close coverage measures to identify verification holes and to show progress towards tape-out.

As a Wireless Design Verification Engineer, you will be part of a team that is responsible for pre-silicon RTL verification of communication subsystems, SoC sub-systems and chip-level functionality. The activity may focus on block level, sub-system level or chip level, including end-to-end simulations of the entire data/control path. You will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.
Description
- Own critical block and sub-system verification of wireless SoC projects
- Architect and develop testbenches and environments, by using state-of-the-art verification methodologies
- Define verification plan, create, simulate and debug test scenarios
- Drive regression and coverage analysis to ensure high quality DV
- Collaborate with design and systems engineering teams to review requirements, specifications and architecture, extract features and define DV attribute

Required V&V Engineer
Job Description Summary
Responsible for running various verification activities on PET medical products that covers multi-disciplinary aspects from SW/HW, electronics, mechanics, physics, image quality and radiation - which is safety for users and monitored by a tag all the time.
Job Description:
Responsible for planning and implementing verification methodologies and ensuring proper fulfillment of system and sub-system requirements.
Responsible for reviewing various product designs, verifying its functionality in agile testing methods.
Responsible to determine the testing environments and tools.
Analyze and debug system failures and issue found during testing, while delivering detailed reports identifying these issues for further investigation.
Work closely with development teams
Non-hybrid, full-time position on site
Flexible on working hour, including 2-3 evening shifts (14:00-23:00) per week as needed
Working on global programs that required tight collaboration with global and Israel teams.

we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters.

As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You wont just execute tasks; you will define the Formal verification strategy for chips that drive the worlds largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications.

Key Responsibilities

Own and develop formal verification environments from scratch through to sign-off
Apply formal verification methodologies and strategies to prove the correctness of intricate designs
Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements
Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs
Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently
Architect and develop generic, common formal functions and properties to be reused across multiple projects

FPGA Verification engineer (6160) We are seeking a talented and experienced FPGA Verification engineer to join our hardware development team. In this role, you will be responsible for defining and executing comprehensive verification strategies for complex FPGA-based systems, from architectural definition through system integration.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of google's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
google system infrastructure builds the cloud for google services and for google cloud customers, by solving business TEST of performance and cost, utilizing hardware, software, and system solutions.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving team behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
plan the verification strategy, identify the platform to validate reasoning components.
define the TEST plan and strategy with stakeholders, including sign-off and exit criteria.
plan and execute the verification of internet protocols (ips) using dynamic verification and formal verification.

in this role, you will work as part of a research and development team. you will build verification components, constrained-random testing, system testing, and verification closure. you will verify digital designs, collaborate with design and Verification engineers on projects, and perform direct verification. you will build constrained-random verification environments that exercise designs through their corner cases and expose all types of bugs. you will manage the full lifecycle of verification which can range from verification planning, TEST execution, or collecting and closing coverage.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
create and enhance constrained-random verification environments using systemverilog or formally verify designs with strategic value add (sva) and industry-leading formal tools.
identify and write all types of coverage measures for stimulus and corner cases.
debug tests with design engineers to deliver functionally correct design blocks.
close coverage measures to identify verification holes and to show progress towards tape-out.