דרושים » חשמל ואלקטרוניקה » V&V Engineer

Required V&V Intern
Job Description Summary
Responsible for running various verification activities on PET medical products that covers multi-disciplinary aspects from SW/HW, electronics, mechanics, physics, image quality and radiation - which is safety for users and monitored by a tag all the time.
Job Description
Responsible for planning and implementing verification methodologies and ensuring proper fulfillment of system and sub-system requirements.
Responsible for reviewing various product designs, verifying its functionality in agile testing methods.
Responsible to determine the testing environments and tools.
Analyze and debug system failures and issue found during testing, while delivering detailed reports identifying these issues for further investigation.
Work closely with development teams
Non-hybrid, full-time position on site
Flexible on working hour, including 2-3 evening shifts (14:00-23:00) per week as needed
Working on global programs that required tight collaboration with global and Israel teams.

Required Senior Manager PET V&V
Job Description Summary
The PET V&V Manager will lead and oversee all Verification and Validation activities for Positron Emission Tomography (PET) systems and components, ensuring product quality, regulatory compliance, and successful product launches within
Job Description
Job Responsibilities:
* Lead and manage a group of 30-40 V&V engineers and technicians, including team leads, with responsibility for hiring, training, performance management, and career development.
* Develop, implement, and maintain comprehensive V&V strategies, plans, and protocols for PET systems, subsystems, and software, adhering to our quality systems and regulatory requirements (e.g., FDA, CE).
* Oversee the execution of V&V activities, including test case development, test execution, defect management, and results analysis, ensuring thorough coverage and traceability to requirements.
* Collaborate closely with R&D, System Engineering, Quality Assurance, Regulatory Affairs, and Project Management teams throughout the product development lifecycle to define requirements, design testability, and ensure V&V deliverables are met on time and within budget.
* Drive continuous improvement in V&V processes, tools, and methodologies, incorporating industry best practices and lessons learned.
* Review and approve V&V documentation, including test plans, reports, and traceability matrices, ensuring accuracy and completeness.
* Participate in design reviews, risk assessments, and post-market surveillance activities to identify potential V&V implications.
* Represent the V&V team in internal and external audits, providing evidence of compliance and addressing any findings.
* Stay abreast of new technologies, industry standards, and regulatory changes relevant to PET imaging and V&V.

FPGA Verification engineer (6160) We are seeking a talented and experienced FPGA Verification engineer to join our hardware development team. In this role, you will be responsible for defining and executing comprehensive verification strategies for complex FPGA-based systems, from architectural definition through system integration.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
in this role, you will work as part of a research and development team. you will build verification components, constrained-random testing, and system testing, and drive verification closure. you will verify digital designs, collaborate closely with design and Verification engineers on projects, and perform direct verification. you will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. you will manage the full life-cycle of verification, which can range from verification planning and TEST execution to collecting and closing coverage.the ai and infrastructure team is redefining whats possible. we empower our customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include, cloud customers, and billions of our users worldwide. we're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for cloud, global networking, data center operations, systems research, and much more.
responsibilities
plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
create and enhance constrained-random verification environments using systemverilog and uvm, or formally verify designs with systemverilog assertions (sva) and industry leading formal tools.
identify and write all types of coverage measures for corner-cases.
debug tests with design engineers to deliver functionally correct design blocks.
close coverage measures to identify verification holes and to show progress towards tape-out.

We are seeking a highly motivated System Engineer to contribute to the design, development, and integration of cutting-edge medical imaging systems. This role involves ensuring system performance, reliability, and compliance with medical standards.
Job Description
Job Responsibilities
Define and analyze system requirements, translating them into detailed technical specifications for hardware and software components.
Participate in the architecture, design, and integration of complex medical Ultrasound imaging systems .
Develop test plans and procedures to verify and validate system functionality, performance, and reliability.
Conduct root cause analysis for system defects and anomalies, implementing effective solutions and preventative measures.
Collaborate with cross-functional teams, including R&D, manufacturing, quality assurance, and regulatory affairs, throughout the product lifecycle.
Perform risk analysis and contribute to the development of mitigation strategies in accordance with medical device regulations.
Support the entire product development process, from concept to post-market surveillance.
Document all phases of the system engineering process, including requirements, design, test results, and issue resolution.
Stay abreast of new technologies and industry trends in medical imaging and system engineering.

As a Wireless Design Verification Engineer, you will be part of a team that is responsible for pre-silicon RTL verification of communication subsystems, SoC sub-systems and chip-level functionality. The activity may focus on block level, sub-system level or chip level, including end-to-end simulations of the entire data/control path. You will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.
Description
- Own critical block and sub-system verification of wireless SoC projects
- Architect and develop testbenches and environments, by using state-of-the-art verification methodologies
- Define verification plan, create, simulate and debug test scenarios
- Drive regression and coverage analysis to ensure high quality DV
- Collaborate with design and systems engineering teams to review requirements, specifications and architecture, extract features and define DV attribute

Required Lead Clinical Applications Engineer
Job Description Summary
The Lead Clinical Applications Engineer is a role within R&D, focused primarily on new product introduction and continuous improvement of post-market PET‑CT imaging systems and related software. The role provides clinical and application expertise to product and engineering teams, ensuring solutions meet clinical needs, deliver strong image quality and quantification, and perform reliably in real‑world use.
Working closely with R&D, system engineering, product management, service, and field teams and customers, this role translates clinical needs, customer feedback, and usage insights into practical system and software improvements, while supporting resolution of complex clinical and application‑related issues.
Job Description
Lead Clinical Applications Engineer - PET‑CT R&D
Key Responsibilities
Serve as a clinical reference for PET‑CT applications and workflows within R&D programs.
Support investigation of selected complex customer or field issues, translating findings into actionable inputs for product improvement.
Interface with product, software, algorithms, system engineering, hardware, UX, service, and field organizations as needed.
Translate clinical use cases and user needs into system and software requirements in collaboration with engineering teams.
Support design and validation of PET‑CT applications, reconstruction methods, and workflow solutions.
Provide clinical input to decisions impacting image quality, quantification accuracy, dose, and user experience.
Participate in evaluation of AI‑enabled PET‑CT features, supporting clinical validation and performance claims.
Contribute to usability, clinical validation, and regulatory‑related documentation as required.

Required V&V Engineer
Job Description Summary
Activities contributing to the design and development of products, solutions and systems. Includes activities linked to technical improvement of existing products and components Impacts quality of own work and the work of others on the team. Executes standard operational/technical tasks typically subject to instructions and work routines. There is latitude to rearrange the sequence to complete task/duties based on changing work situations.
Job Description
Roles and Responsibilities:
Responsible for execution of laboratory and field validation testing, inspection and data acquisition for use in the design and validation of products and services. Responsible for design and construction of test facilities, instrumentation systems and the development of test software
Broadening knowledge of own technical discipline to execute policy/strategy. May include support roles with specialized technical field of knowledge; still acquiring higher level knowledge and skills.
Basic understanding of key business drivers; uses this understanding to accomplish own work. Good understanding of how work of own team integrates with other teams and contributes to the area.
May have some autonomy to make decisions within a defined framework. Resolves issues in situations that require good technical knowledge and judgment within established procedures. Consults more senior team members for issues outside of defined instructions/parameters.
A job at this level requires good interpersonal skills and may be required to lead a junior team. For customer facing roles, develops strong customer relationships and serves as the interface between customer and GE. Explains technical information to others.

in this role, you will work as part of a research and development team. you will build verification components, constrained-random testing, system testing, and verification closure. you will verify digital designs, collaborate with design and Verification engineers on projects, and perform direct verification. you will build constrained-random verification environments that exercise designs through their corner cases and expose all types of bugs. you will manage the full lifecycle of verification which can range from verification planning, TEST execution, or collecting and closing coverage.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
create and enhance constrained-random verification environments using systemverilog or formally verify designs with strategic value add (sva) and industry-leading formal tools.
identify and write all types of coverage measures for stimulus and corner cases.
debug tests with design engineers to deliver functionally correct design blocks.
close coverage measures to identify verification holes and to show progress towards tape-out.

As a Design Verification Engineer, you will be responsible for ensuring "bug-free first silicon" for complex IP and SoC designs. You will drive all phases of pre-silicon verification, from defining methodologies and test plans to RTL freeze and tape-out sign-off. These roles are highly collaborative, requiring close interaction with architecture, design, and software teams across global sites.
Responsibilities
Architect and develop scalable, portable verification environments, including UVM-based testbenches, protocol monitors, agents, and checkers.
Define detailed test and coverage plans based on micro-architecture specifications and extract features for DV attributes.
Create and simulate test scenarios, perform advanced debugging, and conduct end-to-end simulations of data/control paths.
Drive regression and coverage analysis (metric-driven verification) to ensure the highest quality, productivity, and time-to-market.
Partner with architects and designers from the early stages of feature definition to influence IP/SoC specifications.
Apply formal verification, hardware acceleration, and power/performance (NLP) analysis where applicable.