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Youll be joining the post silicon validation team in PHY system group Silicon One group as part of the silicon development .
Our team deals with PHY and system aspects of the SerDes communication IP: PHY FW, calibrations, system definitions and operations and post-silicon validation including developing the automation infrastructure and tools.
We use latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

You will join our team, the epicenter of ASIC design. Our engineers handle every aspect of chip design, from definition and architecture to coding, physical design, and signoff.
Your responsibilities will include:
Responsible for the end-to-end processtaking the system from a cold and dark state to full, reliable operation, including integration, testing, and troubleshooting to ensure system usability and reliability.
Spearhead innovative switch system design, guiding the process from concept through to mass production.
Collaborate with multi-functional teams in areas such as board design, mechanics, thermal, PCB layout, production, software/firmware, RTL, and more.
Act as the technical focal point and decision-maker for the project.
Conduct hands-on testing in a lab environment and support production and qualification stages.
Define product specifications, develop electrical schematics, and guide component selection and layout processes.

You'll join our architecture team, central to silicon development.
You will define features of future devices using the latest silicon technologies, focusing on Logic Design and coding.
You will be responsible for defining the device specification.

You'll join the Front-End Design team , responsible for all chip design processes from definition and microarchitecture to final product.
Our design engineers engage in every aspect of chip design: definition, design, verification, signoff, and validation through to production.
We apply the latest silicon technologies and processes to build the largest-scale and most sophisticated devices, pushing the boundaries of feasibility.

You'll join our architecture team, central to silicon development .
You will define features of future devices using the latest silicon technologies, focusing on Logic Design and coding.
You will be responsible for defining the device specificaton.

You'll be part of our group, the hub of ASIC design.
As a member of our team, you'll contribute to driving our groundbreaking next-generation network devices..
Our unique team operates in a startup atmosphere within a stable and leading corporation.
Our design center is exceptional, hosting all silicon hardware and software development disciplines under one roof.
We are redefining the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all future routing products.
Our devices are crafted to be universally adaptable across service providers and web-scale markets, suitable for both fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale, or feature flexibility.

You will join our , the epicenter of ASIC design.
Our engineers handle every aspect of chip design, from definition and architecture to coding, physical design, and signoff.
Your responsibilities will include:
Spearhead innovative switch system design, guiding the process from concept through to mass production.
Collaborate with multi-functional teams in areas such as board design, mechanics, thermal, PCB layout, production, software/firmware, RTL, and more.
Act as the technical focal point and decision-maker for the project.
Conduct hands-on testing in a lab environment and support production and qualification stages.
Define product specifications, develop electrical schematics, and guide component selection and layout processes.

You'll be joining our Physical Design team which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Static Timing Analysis, Design Floor Planning, Physical Verification.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Join the team and be part of the cutting-edge innovation that drives our next-generation network devices.
Our unique team operates in a startup-like atmosphere within a stable and leading corporation, working on some of the most advanced silicon technologies. Our design center is home to all silicon hardware and software development disciplines, creating an environment that fosters collaboration and technical excellence.
We are redefining the industry and building the next-generation internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation for all of future routing products. we deliver high-speed networking while ensuring programmability, power efficiency, and scalability across a range of service provider and web-scale markets.
Your Impact:
As a Design for Test (DFT) Engineer, you will:
Develop and implement DFT features to ensure high-quality, testable, and manufacturable designs.
Contribute to the full product cycle, from pre-silicon design to post-silicon debug and production qualification.
Work closely with chip architects, design engineers, and verification teams to define and optimize DFT strategies.
Implement ATPG, scan compression, and memory BIST techniques to improve test coverage and efficiency.
Lead debugging and root-cause analysis of silicon failures to improve yield and reliability.
Establish DFT methodologies and best practices to enhance the efficiency of future designs.

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Join the PHY System Team, a key part of silicon development.
You'll be at the forefront of defining, implementing, and validating advanced PHY and system solutions for next-generation network devices.
Your responsibilities will include:
Defining features for future devices utilizing cutting-edge silicon technologies.
Developing and optimizing PHY sequences and calibration processes.
Driving system-level definitions, operations, and post-silicon validation.
Collaborating with cross-functional teams to ensure high-quality deliverables.

Reporting to the Chief Product Officer, you will lead our Carrier Ethernet product line, managing a portfolio that serves telecom carriers, managed service providers, and enterprise customers worldwide.

Responsibilities:

Product Strategy: Define and execute product strategy for BATMs Carrier Ethernet portfolio, targeting 25%+ annual revenue growth.
Roadmap Management: Develop data-driven product roadmaps aligned with MEF standards evolution, customer requirements, and competitive positioning.
Customer Engagement: Conduct quarterly business reviews with top-tier customers including major carriers and service providers.
Requirements Analysis: Partner directly with internal engineering teams and OEM partners to translate customer use cases into technical specifications and product requirements.
Pricing Strategy: Develop competitive pricing models and business cases that balance market competitiveness with profitability goals.
Go-to-Market: Lead product launches and market entry strategies, coordinating across marketing, sales, and channel partner teams.
Technology Vision: Drive technical innovation, including next-generation MEF 3.0 services, SDN integration, and network automation capabilities.