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Required CPU Design Integration Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define and implement solutions for design, integration and verification problems using in-house and external technical solutions or tools.
Involve in project development and convergence with the highest quality, agreement with issues as they arise through design and implementation, or equivalent relevant experience.
Connect between RTL design, physical design, DFT, external IPs and SoC while maintaining project priorities.
Maintain project infrastructure and stability.
Ensure chip quality by implementing best practices and implementing quality control measures.

Required Physical Designer Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with Functional Design, Design for Testing (DFT), Architecture, and Packaging Engineers. Additionally, you will solve technical problems with micro-architecture and logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
Responsibilities
Define and drive the implementation of physical design methodologies.
Take ownership of one or more physical design partitions or top level.
Drive to the closure of timing and power consumption of the design.
Contribute to design methodology, libraries, and code review.
Define the physical design related rule sets for the functional design engineers.

As a DevOps Engineer, you will join a cybersecurity engineering group building a new system at the intersection of cybersecurity and advanced AI.
You will help design, build, scale, and maintain cloud infrastructure that supports cybersecurity tools, orchestration flows, and autonomous AI agents.
You will work closely with development teams, cybersecurity, and product stakeholders to automate processes, improve reliability, and enable fast and secure software delivery.
Key Responsibilities
-Build and maintain scalable AWS-based cloud infrastructure.
-Create and improve CI/CD pipelines, GitOps-based deployments, and automation flows.
-Deploy, manage, and troubleshoot Kubernetes-based workloads.
-Improve infrastructure reliability, scalability, observability, and operational stability.
-Support monitoring, logging, alerting, and operational dashboards.
-Improve resource efficiency and support cloud cost optimization.
-Evaluate and adopt modern cloud-native and DevOps technologies.

Required Senior Design Engineer, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHSIC Hardware Description Language (VHDL)), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Required Senior DFT Lead
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
In this role, you will work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing autonomous solutions that define the next-generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Responsibilities
Drive and execute DFT activities in the design, implementation, and verification solutions for application-specific integrated circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, memory built-in self test (MBIST), and automatic test pattern generation (ATPG).
Collaborate with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Oversee DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

Software Engineer II, Cloud Security SOAR
About the job
Our software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to our needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward.
Responsibilities
Manage the Authorization and Authentication framework for the entire Security Orchestration, Automation and Response (SOAR) platform.
Lead the design and implementation of granular Data Role-Based Access Control, ensuring robust, multi-tenant security and precise data visibility controls for our global enterprise base.
Own the SOAR Settings Page and core platform governance, delivering intuitive, high-performance controls.
Lead and contribute to multiple high-impact AI projects within the Platform. Be a key player in pushing the boundaries of innovation by integrating cutting-edge Generative AI technologies, utilizing our Agent Development Kit (ADK) to build intelligent security agents that assist users in real-time.
Help pioneer the future architecture of SOAR-shaping a platform that transitions beyond static playbooks toward adaptive, self-steering incident response workflows that act independently on behalf of security teams.

Required Software Engineer III, Platform Engineering and Infrastructure
About the job
Our software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to our needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward.
As a part of this team, you will join the premier engineering powerhouse driving Chronicle Security Orchestration, Automation and Response (SOAR) to operate at true scale. As hyper-focused experts in Platform Engineering and Infrastructure, the team holds absolute ownership over the Security Operation provisioning service, orchestrating complex resources in our Cloud Platform and mission-critical workloads in Kubernetes (GKE) and in Compute infrastructure with precision. You do not simply respond to operational issues, but build the platforms, tools, and developer infrastructure that transform complex challenges into robust, software-driven solutions.
Responsibilities
Write product or system development code.
Participate in, or lead design reviews with peers and stakeholders to decide amongst available technologies.
Review code developed by other developers and provide feedback to ensure best practices (e.g., style guidelines, checking code in, accuracy, testability, and efficiency).
Contribute to existing documentation or educational content and adapt content based on product/program updates and user feedback.
Triage product or system issues and debug/track/resolve by analyzing the sources of issues and the impact on hardware, network, or service operations and quality.

Required Senior SOC DFT Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will play a crucial role in Design for Testing (DFT) Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality matrix throughout the project life-cycle, and providing sign-off DFT to tapeout.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs.
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project (e.g., planning, execution, tracking, quality, and signoff).

Join our AI Platform group as an AI Engineer in the AI Core team and help build the next generation of AI-powered networking and security solutions at our company.
The AI Core team is responsible for developing AI applications, intelligent agents, and backend systems that integrate directly into our company products and workflows. As part of our companys strategic AI direction, the team focuses on turning modern GenAI capabilities into scalable production systems that help customers operate, troubleshoot, investigate, and manage complex networking and cybersecurity environments more effectively.
This role combines strong software engineering, modern GenAI technologies, and deep product impact. Youll work on building production-grade AI systems, integrating LLMs and agentic workflows into large-scale products, and helping shape how AI transforms cybersecurity and networking operations across the company.
We are looking for engineers who are excited about building real-world AI systems in production, not just experimenting with models, but designing scalable applications, integrating intelligent agents into complex products, and solving challenging engineering problems with direct customer impact.
Key Responsibilities
Design, develop, and maintain AI-powered applications, agents, and backend systems
Build intelligent workflows and agentic systems integrated into our company networking and security products
Develop scalable APIs, services, and infrastructure supporting GenAI applications in production
Integrate LLMs, RAG pipelines, vector databases, and orchestration frameworks into robust production systems
Collaborate closely with AI researchers, software engineers, infrastructure teams, and product groups to deliver end-to-end AI solutions
Improve scalability, reliability, observability, and operational excellence of AI systems
Explore and adopt modern AI engineering methodologies, frameworks, and tooling
Participate in architectural and technical decisions shaping the future of AI across our company products.

Required Design Team Manager, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design Team Manager within the Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will oversee the Intellectual Property (IP) and SoC VLSI design cycle from architecture to production. You will own and manage IP, subsystems and SoC development, leading a group of designers and design tech leads. You will be responsible for mentoring and developing team members and tech leads, driving improvements in leadership, technical execution, and design flows.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead design activities at IPs, subsystems, and System-on-Chips (SoCs).
Plan, execute, track progress, assure quality, and report status of the assigned activity.
Work closely with internal customers and support multiple activities and deliverables.
Assure and manage deliverables quality at all RTL design categories including reviews, static checks, design for physical design, power, etc.

Required SoC DFT Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a System on a Chip (SoC) Design for Test (DFT) Engineer, you will be responsible for defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design and verify the DFT logic and prepare for post silicon and co-work/debug with test engineers.
Responsibilities
Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT).
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test, Test Access Point (TAP) controller, clock control block, and other DFT IP blocks.
Insert MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

Required RTL Design Technical Lead, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will contribute in all phases of Application-Specific Integrated Circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

At our company, what you do matters. Every day, we protect over 100,000 organizations worldwide from increasingly sophisticated cyber and AI-driven threats, securing their AI transformation.
Our prevention-first approach safeguards hybrid networks, cloud environments, digital workspaces, and AI systems, stopping attacks before they happen.
This is where innovation meets real-world impact. Youll help customers across industries operate with confidence in a rapidly changing digital world, working alongside smart, curious people who take ownership, challenge assumptions, and solve complex problems.
Were proud to be recognized by TIME, Newsweek, and Forbes for excellence and workplace culture.
What really sets our company apart is the opportunity to grow, contribute, and help companies navigate their AI transformation securely.
If youre excited to work at the forefront of AI-driven security on a global scale, this is the place to do it.
Key Responsibilities
We are looking for a Technical Support Engineer to join our Support team and provide high-quality technical assistance to customers and partners.
In this role, you will work with advanced networking and cybersecurity technologies, troubleshoot challenging technical issues, and play an active role in ensuring a reliable and secure customer experience.
You will take part in resolving real-world technical problems across diverse environments, working closely with customers while collaborating with internal teams to deliver effective and professional support.
Major Responsibilites
Provide first-line technical support to customers and partners via chat, phone, and email
Assist customers with basic configuration, troubleshooting, and usage of security and networking solutions
Handle support service requests end-to-end, including proper logging, tracking, escalation, and follow-up
Perform initial fault isolation and analysis for networking and security-related issues
Review logs, traffic captures, and system data to help identify root causes of technical problems
Collaborate closely with senior support engineers and internal teams to resolve customer issues effectively
Follow established troubleshooting methodologies, documentation standards, and best practices
Continuously learn and develop technical skills through training, mentoring, and hands-on experience.

Required Hardware/Silicon Engineering PhD Intern, 2027
Please complete your application before 23rd October 2026.
We encourage you to apply as early as possible as we review applications on a rolling basis.
This internship is intended for students in their second or final year of education in an accredited full-time PhD degree program in Israel. Participation in the internship program requires that you are located in Israel for this role for the duration of the internship program. Interns will be required to be available to work full-time for a minimum of 13 weeks over the Summer 2026 (starting in May, June or July) for the duration of the program. Individuals applying for this position will not be eligible for immigration sponsorship.
About the job
The Cloud and AI Infrastructure team in Israel focuses on building our next-generation systems. The teams work is grounded in creating custom hardware, and as an Intern you'll get to collaborate with engineers from various parts of the organisation to influence the future of Cloud and the AI infrastructure by working on the foundational technology that makes it all possible. This is the hardware that powers everything from Cloud, to our most advanced models like Gemini.
As an intern, you will work on fundamental problems at the intersection of hardware, software, and algorithms. You will collaborate with exceptional engineers and researchers on projects that directly impact our custom silicon portfolio, including general-purpose CPUs, highly specialized AI accelerators like our Tensor Processing Units (TPUs), and complex Systems-on-a-Chip (SoCs). Your responsibilities and projects will be tailored to your expertise and could focus on any part of the system stack. This may include:
Algorithmic Innovation: Developing and analyzing new algorithms that are deeply co-designed with our custom hardware.
Software and Compilers: Building the software stack, compilers, and performance analysis tools that unlock the potential of our unique architectures.
System Architectureand and Modeling: Architecting and modeling future CPUs, TPUs, and SoCs to guide critical design decisions.
Hardware Design and Verification: Contributing to all aspects of silicon creation, from logic design and verification to VLSI physical implementation.
Responsibilities
Responsibilities and detailed projects will be determined based on your educational background, interest, and skills.

Required Package Design/Layout Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of our AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Dive into the architecture and microarchitecture of complex hardware units and features, such as packet processing pipelines and advanced networking capabilities. Develop comprehensive post-silicon validation test plans based on a thorough understanding of the design and specifications.
Write, execute, and debug validation tests using Python and/or C/C++, running on Pre-Si emulation platforms and primarily on the silicon.
Lead the bring-up, troubleshooting, and debug efforts on silicon, identifying root causes of hardware and software issues. Collaborate closely with architects, designers, and other teams to drive bug fixes and ensure feature functionality.
Contribute to the development of test infrastructure and methodologies to improve validation efficiency and coverage. Mentor and guide junior engineers as the team grows.