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Our Imaging Radar group develops innovative high-performance Imaging Radar solutions for ADAS and Autonomous Driving markets.
We are seeking an experienced and independent Technical Program Manager, who will lead a multi-disciplinary cutting-edge projects. The scope of work requires deep technical understanding, detailed planning and tracking of concurrent development activities and effective collaboration with several development teams, different stakeholders and management.
What will your job look like:
Lead all development aspects together with major key customer
Plan, manage and lead the project through all development pashes
Collaborate with cross-functional development teams such as VLSI, RF, System, HW, Algorithms, SW and Validation
Lead program reviews and plans with customers
Identify possible technical or execution problems and risks and drive for solutions
Ensure that product is delivered on time, meeting KPIs and within budget
Report program development progress to senior managers.

Required Experienced SoC Verification Engineer
Which team will you join?
Mobileye EyeC VLSI team - a group designing the chips for Radar systems for ADAS and autonomous cars. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
You will take a central hands-on role in Design Verification.
Define Environment micro-Architect, Implement complex UVM environment, Build vPlan .
Execute coverage implementation.
Be part of external IP verification and Internal custom IP.
Be part of System definition and top-level activity.
Take part in Silicon bring-up.

we are looking for a highly skilled and experienced DFT Lead to take a central role in shaping the DFT implementation for the companys next-generation SoC. As the DFT Lead, you will be responsible for overseeing the development and execution of testing methodologies to ensure the functionality, reliability, and manufacturability of integrated circuits (ICs) and other hardware designs. You will play a critical leadership role in integrating test structures into the design of electronic components, driving efficient testing processes throughout the product lifecycle, from production to deployment and maintenance. This is a key position that will directly influence the success of our projects and the quality of our products.
Responsibilities
Develop DFT methodologies for IC designs, such as scan chains, built-in self-test (BIST), boundary scan, MBIST
Implement and validate DFT features to ensure coverage and quality.
Perform scan insertion, MBIST insertion and ensure architectural spec is met
Generate ATPG patterns for stuck at and at speed, ensure all sequential elements are scannable to achieve high coverage. Generate MBIST patterns and ensure all memories are being covered for defects
Collaborate with design teams to create test strategies and plans that identify potential defects
Perform simulations and verification of DFT designs to confirm functionality and accuracy.
Analyze fault models and optimize for high coverage, including stuck-at, transition, and path delay faults.
Collaborate with test engineers to perform yield analysis and improve DFT methodologies.
Troubleshoot and debug design issues found during testing.
Develop techniques to isolate faults and improve test coverage with minimal impact on design.
Work with cross-functional teams (e.g., design, verification, test engineering) to integrate DFT features effectively.
Document DFT architecture, procedures, and test coverage to support production testing and ongoing improvement.

A world leader in driver assistant systems and autonomous vehicles, is looking for talented silicon validation engineer for the range of its next generation SoCs supporting its radar systems
Our team is responsible for validating our radar SoCs, utilizing Pre-Silicon environments, as well as Post-Silicon platforms.
We are developing fully embedded C++ based validation environment for our needs.
You will be taking part in developing anything from environment and drivers through system modules such as file system, network stack, memory management and more, and up to complex automation tools in both C++ and python.
What will your job look like
Get a deep understanding of our chip hardware IP blocks, both analog and digital.
Develop our validation environment.
Develop, port, or add features to the product drivers using Technical Specs and existing modules.
Define, develop and execute various complex validation scenarios on the SoC.
Debug complex SoC problems using embedded GDB, JTAG probes, going down to signal level using scopes.
Take part in Next Gen SoC's Power-On's and platforms Bring-Up's.
Collaborate with other SW/Embedded and HW/Electrical Validation teams across the company.

Required Experienced RFIC/Analog CAD Engineer
The RFIC/Analog design groups in our Radar organization is responsible for developing the cutting edge Transceivers in mmW frequencies for the best Imaging Radar technology. The design process includes the entire process from specs to productization.
To support these challenging processes, we need a skilled CAD team that will work with the design teams on all design aspects and flows from design environment setups, through design tools implementations and support and to chip level verifications and validation enablement.
We're looking for an Experienced CAD or Design Automation Engineer to develop our RF/Analog design tools/flows and automation flows for the next-generation Imaging Radar chips.
What will your job look like:
Build and support RF/analog design environments
Implement, develop, and maintain design flows, tools and scripts.
Evaluate and explore new automation technologies and advocate for efficiency improvements
Evaluate multiple vendor solutions and guide execution, in the most optimal use, based on design needs
Effectively communicate and support a large number of designers, providing high-quality tools and flows, documentation, and presentations.

Were looking for a Experienced Physical Design Engineer to join the growing Physical Design Team, responsible for developing our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS with horizontal ownership.
Floorplan exploration and collaboration with front-end and architecture teams.
Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification.
Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA.
STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff.

Required Experienced Logic Design Engineer
The EyeC VLSI team specializes in designing advanced radar system chips for ADAS (Advanced Driver Assistance Systems) and autonomous vehicles. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
Design ownership on major blocks/clusters from definition to implementation phase.
Participate in various ASIC activities and flow definition which includes CDC, DFT, Lint.
Design micro-architecture of custom blocks.

We develop high-performance imaging radar for autonomously driving vehicles. The project involves cutting-edge HW, VLSI, mechanics, SW and Algorithms. We are looking for an Experienced Chip Package Design Engineer to be part of our imaging radar HW team.
What will your job look like:
Technical Project lead & Co Design to support the development of IC package with the OSAT, Si, VLSI and System Architecture teams.
Manage co-design meetings with HW, RF and VLSI teams
Design IC packages (e.g., flip-chip, wafer-level, FCBGA) using industry-standard EDA tools (e.g., Cadence APD/SIP, Mentor, Ansys tools)
Manage subcontractors and vendors for development and manufacturing of chip substrate, IC package and IC testing
Simulate high-performance signal/power-integrity chip substrate, including layout, mechanical & thermal simulations
Collaborate and support peer teams from other projects.

We are looking for a Emulation Engineer to join the Radar VLSI team and drive the development of the next generation ASIC Sensors.
What will your job look like:
This role is all about making high-end Emulation environment base on new designs.
Building and integrating complex components, working with cross-functional engineering teams, and making systems that will change the way we drive.
This role requires an engineer who loves challenges and knows how to bring engineering excellence while considering complicated constraints.
You will work with members of a cross-functional talented,
You will lead the Emulation development for the VLSI team.
You will work closely with SW Engineers, Logic Engineers, Verification Engineers, and others.
You will serve as an expert matter for your domain, which has the full responsibility to drive & implement improvements and new ideas.

Required Experienced DFT Engineer
The EyeC VLSI team designs cutting-edge chips for RADAR systems used in ADAS and autonomous vehicles and is looking for an experienced DFT Engineer.
This is a unique opportunity to join a team of top-tier engineers working with the most advanced technologies to develop Autonomous Vehicle (AV) SoCs. Every engineer in our team plays a broad and diverse role, taking on significant responsibilities, being involved in critical development stages, and making a direct impact on the success of our projects.
What will your job look like:
You'll be responsible for the architecture of DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary RTL for the different modules
Verify and Validate your design in GLS
Develop ATPG patterns to the highest requirements of Functional Safety (ISO26262).
Debug and analyze coverage and yield loss
Support production activities and Si debug.

Required Experienced Physical Design Engineer
Which department will you join?
VLSI team - a group designing the EyeQ chips for ADAS and autonomous cars.
The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges
Were looking for a Backend Engineer to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.

we are looking for a Senior GenAI/NLP Algorithm Developer to join us in research and development of our next-generation automatic sports video content engine. If you are passionate about state-of-the-art NLP and Generative AI research we are looking for you!
What youll do:
The teams main focus: NLP & Generative AI.
Research and develop end-to-end real-time solutions for sports content automation using state of the art deep learning algorithms for text, speech, audio and data analysis.
Full R&D cycle, from problem definition and research to implementation and productization with a high level of autonomy.
In addition, part of the role & responsibilities will be:
Design, develop and implement state-of-the-art Generative models, prompt engineering and classical ML/NLP techniques to create high-quality solutions for demanding product-oriented NLP tasks.
Engage in collaboration with product, account, and customer success teams to establish success criteria and convert them into measurable objectives and quantitative measures.
Conduct training and evaluation of models within practical production scenarios.

We are seeking an exceptional Technical Project Manager to join our team.

Responsibilities:

* Participate in a team leading an extraordinary international space program, integrating new satellites and capabilities with state-of-the-art technologies into a unified eco- system.
* Analyze customer requirements, specifications, architectures, and operational concepts.
* Manage projects and contribute to design, development, marketing, and business development efforts.
* Collaborate closely with engineering teams to analyze and solve complex system -level challenges.
* Research new technologies and solutions for next-generation systems.

We are looking for talented Engineers to join our Virtual Platforms team.
Virtual platforms play a crucial role in accelerating the development process by enabling early Software development, System-Level testing, and architectural exploration without the constraints of physical prototypes.

As a Virtual Platform Engineer, you will:
Develop accurate and efficient simulation models of hardware components.
Create and maintain Virtual Platform environments for software development and system-level validation.
Debug and optimize complex hardware-software interactions.