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לפני 2 שעות
Location: Haifa and Tel Aviv-Yafo
Job Type: Full Time
Required SOC Quality and Reliability Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Our data centers are the most advanced in the world. In this role, you will help build the SoCs that power these data centers by driving quality and reliability processes from the integrated circuit perspective. You will create silicon and follow it into the field (and back) to drive improvements for the next generations of chips.
You will have an understanding of IC flows, wafer processing, testing, qualification, yield, reliability, and failure analysis. You will work with various cross functional teams to develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute and test plans. Within the larger organization you will collaborate with global hardware quality and reliability teams, silicon design, validation and engineering teams.The AI and Infrastructure team is redefining whats possible. We empower our customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
Responsibilities
Drive the strategic definition and development of design-for-reliability (DfR) guidelines, collaborating with cross-functional subject matter experts to integrate reliability into early design stages.
Define and lead the development of qualification hardware and test methodologies, managing internal teams and external vendors to ensure silicon and package verification.
Execute comprehensive silicon and package qualification programs (including high-temperature operating life (HTOL), early life failure rate (ELFR), electrostatic discharge/latch-up (ESD/LU), biased highly accelerated stress test (b/HAST), etc.) and conduct failure analysis to resolve quality issues.
Extract and analyze data from qualification programs, high-volume manufacturing, and field returns to identify failure mechanisms and trends for yield and reliability optimization.
Develop and implement physics-based statistical Quality and Reliability models (e.g., ELF, time-dependent dielectric breakdown (TDDB), negative bias temperature instability (NBTI) to predict device failure mechanisms and lifetime behaviors.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Materials Science, Physics, or a related field or equivalent practical experience.
8 years of experience in IC silicon quality or reliability.
Experience leading the product reliability lifecycle from post-tapeout through high-volume manufacturing.
Experience with semiconductor complementary metal-oxide-semiconductor (CMOS) technology, device physics, and failure mechanisms.
Preferred qualifications:
Master's degree in Electrical Engineering, Materials Science, or related field.
Expertise in statistical data analysis using tools such as JMP, Python, or JSL.
Knowledge of design-for-reliability (DfR) rules and implementation techniques.
Familiarity with electrical failure analysis (EFA) and physical failure analysis (PFA) techniques.
Track record with silicon reliability on process nodes and advanced packaging technologies.
This position is open to all candidates.
 
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required SOC Quality and Reliability Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Our data centers are the most advanced in the world. In this role, you will help build the state-of-the-art SoCs that power these data centers by driving quality and reliability processes from the Integrated Circuit perspective. You will have an opportunity to create silicon and follow it into the field and back to drive improvements for the next-generations of chips.
You will have an understanding of Integrated Circuit (IC) flows, wafer processing, testing, qualification, yield, reliability, and failure analysis is expected. You will work with various cross-functional teams to develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute and test plans. You will collaborate with global hardware quality and reliability teams, silicon design, validation and engineering teams.The AI and Infrastructure team is redefining whats possible.
Responsibilities
Lead the strategic definition and development of Design-for-Reliability (DfR) guidelines, collaborating with cross-functional subject matter experts to integrate reliability into early design stages.
Establish and direct the development of qualification hardware and test methodologies, managing internal teams and external vendors to ensure silicon and package verification.
Execute comprehensive silicon and package qualification programs (including high-temperature operating life (HTOL), early life failure rate (ELFR), electrostatic discharge and latch-up (ESD/LU), and biased highly accelerated stress test (b/HAST)) and conduct in-depth failure analysis to resolve quality issues.
Analyze data from qualification programs, high-volume manufacturing, and field returns to identify failure mechanisms and trends for yield and reliability optimization.
Develop and implement physics-based statistical quality and reliability models (e.g., early life failure (ELF), time-dependent dielectric breakdown (TDDB), or negative bias temperature instability (NBTI)) to predict device failure mechanisms and lifetime behaviors.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Materials Science, Physics, or a related field or equivalent practical experience.
4 years of experience in Integrated Circuit (IC) silicon quality or reliability.
Experience leading the product reliability life-cycle from post-tapeout through high-volume manufacturing.
Experience with semiconductor complementary metal-oxide-semiconductor (CMOS) technology, device physics, and failure mechanisms.
Preferred qualifications:
Master's degree in Electrical Engineering, Materials Science, or related field.
Expertise in statistical data analysis using tools such as JMP, Python, or JMP Scripting Language (JSL).
Familiarity with electrical failure analysis (EFA) and physical failure analysis (PFA) techniques.
Knowledge of design-for-reliability (DfR) rules and implementation techniques.
Track record with silicon reliability on process nodes and advanced packaging technologies.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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דיווח על תוכן לא הולם או מפלה
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תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SOC Quality and Reliability Engineer, Cloud
You will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. You will be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Our data centers are the most advanced in the world. In this role, you will help build the state-of-the-art SoCs that power these data centers by driving quality and reliability processes from the Integrated Circuit perspective. You will have an opportunity to create silicon and follow it into the field and back to drive improvements for the next-generations of chips.
As a part of this role, you will have an understanding of Integrated Circuit (IC) flows, wafer processing, testing, qualification, yield, reliability, and failure analysis. You will work with various cross-functional teams to develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute and test plans. You will collaborate with global hardware quality and reliability teams, silicon design, validation and engineering teams within the larger organization.The AI and Infrastructure team is redefining whats possible. We empower customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
Responsibilities
Drive the strategic definition and development of Design-for-Reliability (DfR) guidelines, collaborating with cross-functional subject matter experts to integrate reliability into early design stages.
Define and lead the development of qualification hardware and test methodologies, managing internal teams and external vendors to ensure silicon and package verification.
Execute comprehensive silicon and package qualification programs (including high-temperature operating life (HTOL), early life failure rate (ELFR), electrostatic discharge/latch-up (ESD/LU), biased highly accelerated stress test (b/HAST), etc.) and conduct in-depth failure analysis to resolve quality issues.
Extract and analyze data from qualification programs, high-volume manufacturing, and field returns to identify failure mechanisms and trends for yield and reliability optimization.
Develop and implement physics-based statistical quality and reliability models (including early life failure (ELF), time-dependent dielectric breakdown (TDDB), and negative bias temperature instability (NBTI)) to predict device failure mechanisms and lifetime behaviors.
דרישות:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Materials Science, Physics, or a related field, or equivalent practical experience.
10 years of experience in IC silicon quality or reliability.
Experience leading the product reliability life-cycle from post-tapeout through high-volume manufacturing.
Experience working with semiconductor Complementary Metal-Oxide-Semiconductor (CMOS) technology, device physics, and failure mechanisms.
Preferred qualifications:
Master's degree in Electrical Engineering, Materials Science, or related field.
Expertise in statistical data analysis using tools such as JMP, Python, or JSL.
Familiarity with Electrical Failure Analysis (EFA) and Physical Failure Analysis (PFA) techniques.
Proven track record with silicon reliability on process nodes and advanced packaging technologies.
Deep knowledge of Design-for-Reliability (DfR) rules and implementation techn המשרה מיועדת לנשים ולגברים כאחד.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8718507
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Silicon Test and DFT Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Haifa, Israel; Tel Aviv, Israel.
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.The AI and Infrastructure team is redefining whats possible. We empower our customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
Responsibilities
Collaborate with Architecture, Design and Verification teams to develop new product bring-up, validation, characterization, and qualification strategies and manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Verify test solutions on pre-silicon models (simulation or emulation) and develop Automated Test Equipment (ATE) test modules and binning flows.
Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) in preparation for high-volume manufacturing (HVM), working with ATE vendors and internal cross-functional teams.
Manage product sustainment support, including analyzing volume data, improving test time and yield, assessing test escapees and return merchandise authorizations (RMAs), localizing failures, implementing containment measures, and partnering with design, manufacturing, and quality and reliability teams to identify root causes and implement corrective actions.
Bui
Requirements:
Minimum qualifications:
Bachelor's degree in Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience in test engineering.
Experience in pre-silicon validation, test content generation, automatic test equipment (ATE) program development, and post-silicon enabling from new product introduction (NPI) through high-volume manufacturing.
Experience with ASIC test methodologies (MBIST, ATPG, DFT, SerDes, and sensors).
Experience with Python, Java, C# or C/C++ and Advantest or Teradyne ATE platforms.
Preferred qualifications:
Masters in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
10 years of experience in test engineering, including product engineering.
Experience with CPU/GPU SoC architecture, design, validation and debug.
Experience in advanced testing methodologies and data analysis, including system to tester correlation, yield and test time analysis and improvement, etc.
Demonstrated expertise in developing automations for pre-silicon verification and post-silicon test-generation/test-program domains.
Inquisitive and motivated to venture into, and improve, all aspects of post-silicon testing from definition to realization.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8717575
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
לפני 3 שעות
חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior Test Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our data centers are the most advanced in the world. In this role, you will help to manufacture the SoCs that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high-volume manufacturing at wafer fabrications and Outsourced Semiconductor Assembly and Tests (OSATs). You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next-generation of chips. You will help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices. You will drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will need to have a strong understanding of Integrated Circuit (IC) flows, wafer processing, testing, qualification, diagnostics, and failure analysis. You will work with various groups to deploy screening methodologies and flows for data processing, analytics and diagnostics. You will drive the release of cost effective production test solutions into mass production to hit yield and quality goals.The AI and Infrastructure team is redefining whats possible. We empower our customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
Responsibilities
Develop and implement high-volume manufacturing strategies for SoC products, optimizing ATE/SLT test coverage, reduce Defective parts per million (DPPM) and test costs, and manage product data integration.
Accelerate mass production via test program releases, data analytics, lot disposition, test time reduction, yield improvement, and return merchandise authorization (RMA) handling.
Partner with cross-functional teams (Test, Quality, Packaging, Operations) to deploy and maintain high-volume manufacturing (HVM) screening solutions.
Manage database integration for wafersort, final test, SLT, and burn-in, while overseeing test program integration, production release, binning, manufacturing flow definition, NPI material handling, and foundry process optimization.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in product engineering or test engineering.
1 year of experience in people management, developing employees.
Experience with product engineering, supply chain data analytics or diagnostics for manufacturing or New Product Introduction (NPI).
Preferred qualifications:
Experience with industry standards, design tools, and design for testing (DFT) best practices, including at-speed transition delay fault (TDF), automatic test pattern generation (ATPG), memory built-in self-test (MBIST), memory repair, diagnostic tools, and yield improvement.
Experience with product engineering, supply chain data analytics and diagnostics for High Volume Manufacturing and NPI.
Experience evaluating customer returns with ATE and SLT, identifying coverage gaps, developing incremental structural and functional patterns to address quality issues, Statistical analysis (e.g., JMP), Yield Management Systems (e.g., Exensio, YieldExplorer, JMP), and Python for data analytics.
Understanding of skew lot definition, data collection, characterization, data analysis and report.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8720618
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
לפני 2 שעות
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SoC Hardware Quality and Reliability Engineer
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Responsibilities
Own technical specifications, architectural definitions, and physical power-on of custom qualification vehicles (HTOL load boards, ESD fixtures, latch-up rigs). Drive external layout vendors to achieve seamless electrical correlation with ATE environments.
Govern execution quality of applied stresses, define electrical, thermal, and telemetry parameters on test vehicles to ensure uniform, valid stress profiles without unintended overstress or setup artifacts.
Lead the end-to-end engineering delivery lifecycle for qualification hardware, map and drive critical cross-functional dependencies across internal validation and product engineering teams to ensure on-time readiness.
Serve as the primary technical interface for external PCB layout houses, fabrication shops, and component suppliers; manage design reviews, track lead times, and enforce delivery schedules.
Lead laboratory troubleshooting for qualification hardware anomalies; isolate setup/socket faults from true silicon failures and drive supplier corrective actions (CAPA) when board excursions occur.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, related fields, or equivalent practical experience.
8 years of experience in hardware engineering, with a focus on authoring technical specifications, reviewing electrical layouts, and driving verification of semiconductor tests or validation platforms.
Experience driving deliverables and managing quality standards with external layout vendors, board design houses, or hardware component suppliers across multiple global geographies.
Experience working within specialized semiconductor reliability or test laboratories including configuring component Burn-In ovens, high-power stress load boards, ESD simulators, and Latch-Up test setups.
Experience managing engineering hardware delivery schedules, tracking cross-functional milestones, and meeting New Product Introduction (NPI) timelines.
Preferred qualifications:
Master's degree in Electrical Engineering, Materials Science, or related fields.
Experience managing the design execution cycle of complex multi-layer test vehicles through third-party design houses or layout vendors from concept sign-off to laboratory delivery.
Experience defining and verifying electrical correlation baselines between environmental stress setups and High-Volume Manufacturing (HVM) ATE environments.
Deep familiarity with JEDEC silicon qualification hardware standards and how they dictate physical board testing constraints.
Strong background analyzing the quality of stress factors, including power distribution networks (PDN), signal integrity degradation across extended thermal loops, and transient load behavior during reliability cycles.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8721024
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Physical Design Lead, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, youll work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
Youll be part of a team that pushes boundaries, developing, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You'll contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Responsibilities
Lead physical design of complex SoC to tape-out while working with multiple team members.
Evaluate and develop physical design methodologies and decide on the SoC flow.
Work with architects and logic designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design tradeoffs for physical design closure.
Participate in design reviews and track issue resolution, and engage in technical and schedule tradeoff discussions. Create execution plans for projects and manage team efforts from concept to working silicon in volume.
Understand architecture and design specifications with the larger team, and define physical design strategies and tactics to meet quality and schedule goals.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
Experience in silicon implementation and chip integration.
Experience in ASIC development teams.
Experience in managing physical design teams working on digital designs that produce and deliver silicon.
Preferred qualifications:
Experience in extraction of design parameters and analyzing data trends.
Experience and breadth in engineering across physical design, top-level implementation, GDS tape-out.
Experience in top-level floor planning, block integration, static timing analysis, and sign-off.
Understanding of circuit design, device physics, and deep sub-micron technology.
Knowledge of delivery of high complexity silicon in technology process nodes.
Ability to lead cross-functional teams.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8718525
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שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required SoC Test Engineer Lead, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our data centers are the most advanced in the world. In this role, you will help to manufacture the SoCs that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high volume manufacturing at wafer fabs and Outsourced Semiconductor Assembly and Tests (OSATs). You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next generation of chips. You'll help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices. You will drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will need to have a strong understanding of IC flows, wafer processing, testing, qualification, diagnostics, and failure analysis. You will work with various groups to deploy screening methodologies and flows for data processing, analytics and diagnostics. You will drive the release of cost effective production test solutions into mass production to hit yield and quality goals.
Responsibilities
Develop and implement strategies for high volume manufacturing of SoC products, including troubleshooting, ATE test coverage optimization, defective parts per million reduction, test cost reduction, power and performance assurance, and product data integration and correlation between system, ATE, and SLT.
Drive volume ramp and mass production through test program releases, volume data analytics, lot disposition, extended test time reduction, yield improvement, and return merchandise authorization handling.
Drive product leadership for silicon engineering organization from architectural definition to global availability.
Collaborate with cross-functional teams across the globe including ATE and SLT test engineering, quality and reliability, packaging, supplier management and operations to build, deploy, and maintain a high volume manufacturing screening solution.
Manage database integration and advanced usage for wafersort, final test, SLT and burn-in, test program integration, optimization, release to production, binning handling upon need.
דרישות:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in product engineering or test engineering.
3 years of experience in people management, developing employees.
Experience with product engineering, supply chain data analytics or diagnostics for manufacturing or New Product Introduction (NPI).
Preferred qualifications:
Experience with industry standards, design tools, and DFT best practices, including at-speed TDF, ATPG, MBIST, Memory Repair, diagnostic tools, yield improvement.
Experience with product engineering, supply chain data analytics and diagnostics for High Volume Manufacturing and NPI.
Experience evaluating customer returns with ATE and SLT, identifying coverage gaps, developing incremental structural and functional patterns to address quality issues, Statistical analysis (e.g., JMP), Yield Management Systems (e.g., Exensio, YieldExplorer, JMP), and Python for data analytics.
Understanding of skew lot definition, data collection, characterization, data analysis and המשרה מיועדת לנשים ולגברים כאחד.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8719115
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior DFT Lead
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
In this role, you will work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing autonomous solutions that define the next-generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.The AI and Infrastructure team is redefining whats possible. We empower our customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
Responsibilities
Drive and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Collaborate with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Oversee DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
8 years of experience in Design For Test from DFT architecture to post-silicon production support.
4 years of experience with people management.
Experience with DFT design and verification for multiple projects, DFT specification, definition, architecture, and insertion.
Experience with DFT techniques and common industry tools, DFT and Physical Design flows, and DFT verification flow.
Experience in leading DFT activities throughout the ASIC development flow.
Preferred qualifications:
Master's degree in Electrical Engineering or a related field.
Experience in post-silicon Debug, test or product engineering.
Experience in Joint Test Action Group (JTAG) and Internal JTAG (iJTAG) protocols and architectures.
Experience in SoC cycles, silicon bring-up, and silicon debug activities.
Knowledge of fault modeling techniques.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8718728
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דיווח על תוכן לא הולם או מפלה
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
לפני 4 שעות
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Electrostatic Discharge Engineer
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Electrostatic Discharge (ESD) Engineer, you will be responsible for designing, implementing and maintaining measures to prevent and control electrostatic discharge from electronic components and devices. The role involves analyzing, evaluating and mitigating potential ESD-related on die risks for advanced silicon technologies.
Responsibilities
Develop and implement ESD control plans and procedures for new silicon products.
Evaluate ESD risks associated with different stages of product design, manufacturing and handling, and recommend mitigation strategies to ensure compliance with industry standards.
Manage simulation tools such as: PERC (mentor), path finder (ansys).
Know ESD design rules and industry standards.
Collaborate with cross-functional teams to identify and resolve ESD-related issues in products and processes.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical or Electronics Engineering, a related field, or equivalent practical experience.
8 years of experience in ESD control in a manufacturing or product development environment.
Experience in ESD hazards and techniques for preventing and controlling static electricity.
Experience scripting in TCL or Python.
Preferred qualifications:
Masters degree in Electrical Engineering, or a related field.
Experience in chip reliability.
Ability to work independently and as part of a team.
Strong problem-solving skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8720592
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required SoC Test Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Collaborate with Architecture, Design and Verification teams to develop new product bring-up, validation, characterization, and qualification strategies and manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Verify test solutions on pre-silicon models (simulation or emulation) and develop ATE test modules and binning flows.
Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) in preparation for high volume manufacturing (HVM), working with ATE vendors and internal cross-functional teams.
Product sustain support, including volume data analysis, test time and yield improvements, assess test escapees and Return Merchandise Authorization (RMAs), localize failures, implement containment measures and partner with design, manufacturing, quality and reliability teams to root cause and implement corrective actions.
Develop tools, flows and methodologies to continuously improve and automate the testing life cycle.
Requirements:
Minimum qualifications:
Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
4 years of experience in test engineering.
Experience in pre-silicon validation, test content generation, ATE program development, and post-silicon enabling from New Product Introduction (NPI) through High Volume Manufacturing (HVM).
Experience in Python, Java, C# or C/C++ and Advantest or Teradyne ATE platforms.
Experience with ASIC test methodologies (e.g., mbist, atpg, dft serdes, sensors).
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
10 years of experience in test engineering, including product engineering.
Experience with CPU/GPU SoC architecture, design, validation and debug.
Experience in advanced testing methodologies and data analysis, including system to tester correlation, yield and test time analysis and improvement, etc.
Expertise in developing automations for pre-silicon verification and post-silicon test-generation/test-program domains.
Ability to venture into, and improve, all aspects of post-silicon testing from definition to realization.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8718463
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