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We are looking for a Senior Software/Firmware Architect to join our Host Management group. The architect will develop the next-generation management solutions for our networking infrastructure environments. We are a team that values technical depth, clear ownership, and respectful collaboration. We believe great architecture is built through curiosity, rigorous thinking, and close partnership across disciplines. We welcome architects who bring different perspectives, ask hard questions, and want to build systems that matter at scale.

Our team handles the software and firmware that support host management flows throughout platform control software, baseboard management controllers, hardware interfaces, data monitoring, restoration processes, energy regulation, module management, and system orchestration. In this role, you will develop architecture, lead multi-departmental teams, and convert complex platform requirements into scalable, reliable, production-ready solutions.

What you will be doing:

Lead architecture definition for Host Management SW and FW across our networking platforms.

Define system flows across host software, embedded firmware, BMC, device firmware, and hardware interfaces.

Guide the development of architecture for telemetry, recovery, power management, module management, firmware update flows, and control protocols.

Convert product, customer, and platform needs into clear technical specifications and implementation plans.

Work closely with SW, FW, HW, validation, program, architecture, and customer-facing teams.

Provide technical leadership to engineers implementing complex cross-domain features.

Own architecture documentation and communicate technical direction clearly to engineering and leadership.

Our Networking System Product Engineering group is looking for an excellent Software Engineer.  The position requires an understanding of HW and SW to provide stable, efficient, smoothly running production tests, to enable high availability, while ensuring the quality of the products being shipped to customers. You will lead the development of our products and raise the bar of the software development quality in the group. We have crafted a team of extraordinary people, whose mission is to push the frontiers of what is possible today and define the platform of tomorrow.

What youll be doing: 

Design and develop automated tests for networking Switches and Adapters while working closely with the HW, ASIC, and SW Engineering teams to achieve a reliable test with high coverage.

Exposed to various aspects of design, DFT, and test of our next-generation network products.

Take a significant part in the definition and development of tests from the development level to the final test of Network-Systems.

Utilize test suites to find, debug and resolve problems with production process.

Ability to drive projects to full execution in time and working under pressure of schedule and multi project environment.

Supporting and fixing bugs of existing code. Supporting production lines for: deployments, patches, maintenance.

Test Verification and Validation (both HW and SW). Troubleshooting and streamlining/optimizing our testing procedures.

We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today, such as car and Pharmaceutical. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:

Define the NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).

Research of various solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.

Developing models for simulations and performance testing, analysing the results and development of future HW and SW.

Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

Our Networking IC Product Engineering team is looking for a Post Si Characterization and Validation engineer, to take part of Network ASIC, SOC and SiPh ICs characterization efforts of speed, logic, memory, power and analog circuits both using ATE and system level testing. We are in need of hardworking and motivated engineers. Do you have passion for data analysis, post-Si hand on work and problem solving? We will be happy to have you on our team!


What you'll be doing:

The position includes taking ownership of characterization of IC performance and power parameters, developing new characterization and analysis capabilities, enabling the qualification of new and improvement of future products. You will define and build the required tests, perform the analysis and present the results and conclusions to a wide forum including leading designers and high-level executives.

Take important part in definition of requirements for post-SI validation, as well as IC power and performance characterization.

We offer an exciting work environment, with many new learning experiences and interactions with people from different aspects of the company. Our company employs some of the best engineers in the communication field from all across the world, working on innovative technology and developing new and daring projects.

We are searching for hardworking engineers, that will lead new projects starting from the product definition phase, until the mass-production phase, working closely with several other teams, including chip design, power architecture, and BE.

Our Networking IC Product Engineering team is looking for a Post Si Characterization and Validation engineer, to take part of Network ASIC, SOC and SiPh ICs characterization efforts of speed, logic, memory, power and analog circuits both using ATE and system level testing. We are in need of hardworking and motivated engineers. Do you have passion for data analysis, post-Si hand on work and problem solving? We will be happy to have you on our team!

What you'll be doing:

The position includes taking ownership of characterization of IC performance and power parameters, developing new characterization and analysis capabilities, enabling the qualification of new and improvement of future products. You will define and build the required tests, perform the analysis and present the results and conclusions to a wide forum including leading designers and high-level executives.

Take important part in definition of requirements for post-SI validation, as well as IC power and performance characterization.

We offer an exciting work environment, with many new learning experiences and interactions with people from different aspects of the company. Our company employs some of the best engineers in the communication field from all across the world, working on innovative technology and developing new and daring projects.

We are searching for hardworking engineers, that will lead new projects starting from the product definition phase, until the mass-production phase, working closely with several other teams, including chip design, power architecture, and BE.

We are looking for a performance modeling engineer to join the team and shape, optimize, and explore our future networking chips and solutions. The role is cross-disciplinary, collaborating with hardware, software, and research teams across the wider company. You will lead workgroups towards technical solutions that will influence the heart of cutting-edge networking products. You will solve complex problems, develop innovative solutions and be instrumental in determining the architecture of our next generation of networking solutions.

What you'll be doing:
Thoroughly understand our networking solutions across all performance related aspects.
Develop a C++ simulation model to define and evaluate architectural options for our next generation of networking products.
Understand different trade-offs related to solving performance bottlenecks.
Collaborate and lead technical solutions within architecture, uarch, hardware and software teams.
Analyze and model the communication patterns of key DL, GAI, inference, and training applications.
Explore innovative ideas to improve and optimize our chip systems performance.

The System-On-Chip (SOC) group is looking for a strong RTL Design Engineer to own the SOC clocking logic for our next-generation networking chips. Clocks are the backbone of the SOC. In this role you will own the clock generation, distribution, and control logic for the entire chip - PLL and reference clock integration, clock muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on.

This is an RTL design role, not a circuit or transistor-level design role. You will translate micro-architecture specifications into high-quality synthesizable RTL, and drive that RTL through to silicon in close partnership with the micro-architecture, Design Verification, and Physical Design (backend) teams. You will also interact with CAD, Package Design, Software, and DFT teams.

What you'll be doing:

Owning the SOC clocking logic end to end: writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization, from micro-architecture specification through tape-out.

Defining and implementing the SOC clock and reset architecture together with the micro-architecture team - collecting clocking requirements from every unit on the chip and turning them into a coherent, verifiable design.

Owning clock domain crossing infrastructure and CDC closure across the SOC.

Partnering with the micro-architecture team to review specifications, close on design intent, and provide feedback on implementation cost, timing, area, and power.

Working hand-in-hand with the Physical Design (backend) team on clock tree implementation and constraints, partitioning, floorplan and timing feedback, trial synthesis, congestion and timing convergence, and physical design readiness.

Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows.

Driving design quality: lint, CDC/RDC, formal checks, synthesis QoR, connectivity and structural checks.

Supporting SOC-level chip build and assembly, and developing/deploying automation flows that make RTL integration and design quality checking repeatable and scalable.

Supporting emulation, firmware, and post-silicon bring-up customers of your design.

The System-On-Chip (SOC) group is looking for a Senior RTL Design Engineer to serve as the technical lead for clocks development on our next-generation networking chips. Clocks are the backbone of the SOC. In this role you will lead the development of the chip's clocking logic - PLL and reference clock integration, clock generation, distribution, muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on.

This is an RTL design and technical leadership role, not a circuit or transistor-level design role. Working from the clock architecture defined with the architecture and micro-architecture teams, you will lead its implementation in RTL, guide other engineers contributing to it, and drive it through to silicon in close partnership with Design Verification and Physical Design (backend). You will also interact regularly with CAD, Package Design, Software, and DFT teams.

What you'll be doing:

Acting as the technical lead for SOC clocks development - leading the implementation of the clocking logic from specification through tape-out and bring-up.

Working with the architecture and micro-architecture teams on the SOC clock and reset scheme: collecting clocking requirements from units across the chip, feeding back implementation and timing considerations, and translating the agreed scheme into a verifiable design.

Writing and reviewing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization.

Leading and mentoring other RTL engineers working on clocking: reviewing designs, setting coding and quality standards, and distributing work across the team.

Working hand-in-hand with the Physical Design (backend) team on clock tree implementation, SDC/timing constraints, partitioning, floorplan feedback, trial synthesis, and timing convergence.

Partnering with Design Verification on clocking testplans, functional and gate-level debug, and coverage closure.

Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows.

Representing clocking implementation in cross-functional design reviews with architecture, PD, DV, DFT, and CAD stakeholders.

The Networking Application Engineering team is looking for an experienced networking engineer, with wide knowledge in networking systems with focus on physical layers, to join the team and support groundbreaking technology. As a AI Networking Application Engineer one will have a real impact on the business, while working closely with our customers and R&D teams.

What youll be doing:

Gain our customers trust and understand their needs.

Support new supercomputers and AI fabrics technologies.

Solve complex issues while leading highly visible customer issues.

Work closely with various R&D teams and develop features for our customers.

Provide constructive feedback to engineering and marketing regarding products requirements.

We are looking for an experienced Team Lead for the NIC FW verification infrastructure team. In this role, you will lead the verification infrastructure - ensuring testing infrastructure stability, scalability, and continuous improvement - while guiding the development of advanced modules and methodologies. You will be responsible for driving the teams technical direction, supporting the evaluation of data and control path for new features, and ensuring high-quality deliverables that meet the expectations of industry-leading customers. As a leader, you will mentor and grow a team of engineers, foster a culture of ownership and execution, and collaborate closely with NVIDIAs networking NIC FW teams.

What you will be doing:

Lead and drive team execution end-to-end, combining managerial ownership with hands-on technical contribution - including ownership of the verification testing domain, its flows, coverage and the regression cycle.

Develop deep expertise in NVIDIA technologies, with a strong focus on FW functionality with corresponding interfaces with HW and SW.

Drive team execution by setting clear priorities, removing blockers, and ensuring high-quality, timely delivery - while maintaining a high bar for technical excellence and clearly communicating priorities, trade-offs, and status to stakeholders.

Define and continuously improve testing methodologies, including leading retrospectives for missed bugs to identify gaps - driving actionable changes to test coverage, flows, and verifiers.

Act as a technical leader within the team, contributing to design discussions, mentoring engineers, and actively participating in high-level design and code reviews.

We are looking for an outstanding engineer to join our software architecture group and help shape the next generation of our networking products, SmartNICs, and DPUs. In this role, you will work closely with system architects, software/firmware engineers, hardware designers and product stakeholders to define component-level and system-level solutions for advanced datacenter platforms.

You will join a team working at the intersection of AI networking, virtualization, operating systems, security, management, and programmable acceleration. Our mission is to push the boundaries of modern datacenter infrastructure and help define the platforms of tomorrow.

What Youll Be Doing:

Work with architects and engineers to define software architecture for our networking devices, SmartNICs, and DPUs.

Analyze system requirements across networking protocols, virtualization, operating systems, security, management, and services.

Research new ideas, evaluate design alternatives, and build proof-of-concept models, simulations, and prototypes.

Collaborate with software, firmware, and hardware teams on HW/SW co-design, performance, scale, and resource-utilization challenges.

Learn complex datacenter technologies and turn them into clear architecture proposals, design documents, and technical presentations.

We are looking for an outstanding Senior Networking Software Architect to join the NIC/DPU Software and Firmware Architecture group. In this role, you will help define the next generation of our datacenter and AI networking platforms, with focus on DPU management, QoS, performance, telemetry, and software architecture across stacks. You will work closely with hardware designers, firmware/kernel driver teams, system engineers, validation, product management and customers. The role spans early architecture definition, pre-silicon design, bring-up, and production readiness for large-scale AI and cloud datacenter deployments.

What Youll Be Doing:

Own software and system architecture for next-generation DPU management, QoS, performance, telemetry, and observability features.

Define end-to-end control and management flows across DOCA, host drivers, embedded firmware, BMC, management controllers and external management systems.

Specify telemetry and observability requirements, including counters, logs, traces, events, health monitoring, debug data, and streaming telemetry.

Define management interfaces and APIs for configuration, provisioning, lifecycle operations, diagnostics, and field serviceability.

Write clear architecture specifications, interface definitions, flow diagrams, and design documents for software, firmware, and system teams.

Partner with R&D teams to translate high-level architecture into implementable designs and guide features through development, validation, silicon bring-up, and production.

Analyze system performance bottlenecks, interoperability issues, telemetry gaps, and customer-reported issues, then feed learnings into future architecture.

Collaborate with system and cluster architects to ensure NIC/DPU features fit end-to-end AI datacenter and cloud networking designs.

We are seeking a highly skilled and versatile Performance Research and Analysis Manager to join our Performance Group. This role will drive end-to-end performance strategy and execution for next-generation our data centers and solutions based on GPU systems, NIC, Switch, DPU and Networking technologies. The ideal candidate will oversee, evaluating, and optimizing end-to-end AI GPU cluster-level performance for scaling out large scale distributed training and inference jobs communication. The role will focus heavily on RDMA, Networking Protocols, Collective Communication, Congestion Control, and Load Balancing algorithms. Secondarily, you will lead our DPUs and Storage technologies for N-S use cases to support AI Inference jobs. Third, you will drive our Performance Dashboards and Observability for cluster-level performance analysis from a stream line telemetry across NICs, Switches, GPUs, and NVlink.

What you'll be doing:

Drive end-to-end performance strategy, characterization, test plans, and optimization for next-generation our AI GPU clusters, focusing on large-scale distributed training and inference workloads.

Deeply evaluate and optimize our Networking core technologies performance, including RDMA/PRDMA, networking protocols, collective communication (NCCL), congestion control, and load-balancing algorithms.

Work on performance research and analysis of NVIDIA DPUs and storage technologies in North-South (N-S) use cases and deployment scenarios to maximize performance and efficiency for AI inference jobs.

Drive the strategy for performance observability and dashboards across next-generation NVIDIA data center solutions and supercomputers by leveraging scalable, streamlined telemetry pipelines to build performance dashboards and automated analytics based on real-time performance metrics across NICs, Switches, GPUs, and NVLink boundaries.

Perform deep root-cause analysis (RCA) on complex multi-node performance bottlenecks, driving actionable mitigation plans across hardware, firmware, and software teams.

We are seeking a Senior System Management Architect to lead the management architecture for our advanced SmartNIC cards. You will be the resident expert for SmartNIC system management, ensuring that NIC ASICs, Baseboard Management Controllers (BMCs), MCUs, CPUs, and CPLDs operate in perfect unison. You will own the lifecycle management specifications for SmartNIC platforms-from factory provisioning and day-one deployment to complex orchestrated reset flows and secure recovery. If you are someone who enjoys looking at a high-level system diagram and then immediately diving into the I2C/I3C bus topologies and PLDM command structures required to make it work, this role is for you.

What you'll be doing:

System Architecture & Flow Definition: Define and document comprehensive production, provisioning, update, recovery and reset flows for SmartNIC cards. Crucially, you will ensure that these board-level architectural decisions perfectly align with and support overarching platform-level needs, orchestrating seamless coordination between the NIC ASIC, BMC, CPU, and peripheral components.

Security & Provisioning: Specify security provisioning flows including OTP fusing, secure boot enablement, attestation key injection, certificate chain management, RPMC key derivation, and PQC (Post-Quantum Cryptography) requirements. Define IPN-to-OPN transition and component locking procedures.

Protocol Implementation & Guidance: Specify the use of standard management protocols (MCTP, PLDM, SPDM, NC-SI) across internal board interfaces to achieve secure boot, firmware updates, and telemetry gathering.

Hardware/Software Intersect: Dive deep into device-level hardware and software behaviour. Define CPLD logic requirements, power-sequencing dependencies, and reset orchestration (e.g., handling PCIe PERST#, SBR, and forced resets) for multi-host and standalone SmartNIC environments.

Interface Management: Architect intra-board communication pathways using PCIe, I2C/I3C, USB, and SPI, ensuring robust out-of-band (OOB) and in-band management connectivity.

Cross-Functional Leadership: Collaborate tightly with Production teams, Hardware and Firmware Engineering, NIC FW/Driver teams, and QA to translate your architectural specifications into implementable, testable realities.

Technical Documentation: Author rigorous technical specifications, test plans, and architectural design documents to guide both development and factory production.

Our Networking Product Engineering is looking for a Development Quality Manager to join the NPE management team and lead quality methodology across a broad engineering organization.

In this role, you will define and drive the quality operating model across product development, design, validation, NPI, manufacturing transfer, and field-learning interfaces. You will work across teams that develop products as well as internal engineering deliverables such as test boards, testers, and validation infrastructure, ensuring that quality is designed in from concept through production and beyond.

This is a high-impact leadership role for someone who can combine engineering depth, structured quality methods, and strong cross-functional influence.

What youll be doing:
Lead quality activities throughout the product lifecycle, from concept through NPI and manufacturing transfer.
Define and improve development quality processes and frameworks across design, engineering, test, and V&V.
Participate in design reviews, providing quality input and milestone-readiness guidance.
Lead risk management activities, including FMEA and preventive quality methods.
Drive root-cause investigations and ensure effective CAPA implementation and closure.
Define, monitor, and report quality KPIs to NPE leadership.
Collaborate with R&D, reliability, manufacturing, supply chain, and operations partners.
Support audits and ensure compliance with internal and external requirements.
Serve as the primary NPE interface to Hardware and Operations Quality teams, driving organizational learning and governance across test assets.