This role is for a analog IP lead who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of silicon development from definition to high quality production.
Specifying requirements and circuit architecture for analog blocks and sub-blocks of an IP, lab bring-up, characterization and debug, write specifications, test plans and characterization reports, work with chip design teams, system HW and SW design teams, ATE PE.
You will be responsible for:
Develop the circuit design of the IPs analog blocks following established design guidelines based on microarchitecture spec. Own all aspects of circuit design development.
Work and collaborate with other designers in the group to deliver results.
Work with FE & BE teams to ensure quality analog integration.
Work with power/performance and functional verification team to define and validate operation sequences.
Work with multi-disciplinary teams to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process.
Work with post silicon validation groups to ensure the design meets the power/performance targets.
Requirements: Minimum Qualifications
5+ years experience in analog IC design.
Deep understanding of transistor device characteristics.
Deep understanding of power, performance and area trade-off in mixed-signal designs.
A proven track record of high-performance designs in high volume production for low power applications.
Knowledge of analog IC design flow and tools.
Strong communication skills are a must, as the candidate will interface with a lot of different groups within the company.
Excellent social and interpersonal skills.
Hands-on design expertise in one or more of the following areas: High Speed, Low Power I/O Circuit Design: familiarity with PHY principles and concepts including forwarded clock topologies, training and calibration schemes etc.); High Speed Clock Path: low jitter distribution, DCD correction, phase shift (through delay lines or phase interpolation); Analog Front End: low noise and high-resolution signal conditioning prior to ADC and Op-Amp, switched-cap and continuous time filters, reference/bias generation, LDO etc.; Data Conversion: ADC and DAC subsystem. Different styles of data converters (ΔΣ, SAR, pipelined, SAR and flash) and associated calibration techniques.
Strong initiative and ownership of responsibilities, productive.
Ability to work well in a team and be productive under tight schedules.
Experience with advanced FinFET CMOS processes - an advantage.
Preferred Qualifications
B.Sc. in Electrical Engineering.
MS.c\ PhD - advantage.
This position is open to all candidates.