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We are looking for best-in-class Chip Design Verification Engineer to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What youll be doing:

Work as a Chip Design Verification Engineer as part of a combined design and verification team that develops front-end design for the Switch silicon, GPU and HCA.

Plan and Design Verification units/blocks according to Arch & Micro arch specifications under challenging constraints with high orientation to power, area, and performance.

Work closely with multiple teams within organizations such as Architecture, Micro-Architecture, and FW-interaction with organization-wide groups.

We are looking for an excellent Firmware Design Engineer for NVIDIA FW PHY Group. The person will closely work with NVIDIA FW development, architecture, chip design teams and gain deep understanding of NVIDIA's Networking products and technologies. We have some of the most forward-thinking and hardworking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best chip design team in the industry!

What youll be doing:

Working on the most Ground breaking technology for building AI infrastructure.

Design and develop PHY-layer firmware for our latest networking devices, improving performance and reliability in our next-generation products.

Enabling new SerDes and physical linkup flows.

Work closely with the architecture, HW, and SW design teams.

Define implement and maintain FW algorithm to control the Silicon.

Develop and test FW on emulation & simulation environments during the Pre-silicon phase.

Debug and screen HW/FW/SW issues.

Take an active part in silicon bring-up and SW development phases.

Lead data-driven discussions about the product functionality and areas for improvement.

Our work in Networking and AI is transforming the world's largest industries and profoundly impacting society. Our Networking product security team is looking for an outstanding technical AI red teamer with hands-on safety and security experience to help us improve the safety posture of AI models, systems and infrastructure. In this role you will reduce risk, threats, and vulnerabilities in our networking AI products.

What you'll be doing:
Drive hands-on safety and security research on a range of AI and networking products.
Develop tools and processes to expose novel weaknesses in AI models and systems to preempt threats.
Participate in defining and ensuring AI development processes meet safety and security standards.
Partner with cross-functional teams to understand needs and implement solutions.
Be a technical focal point across multiple teams and provide hands-on AI safety, security and engineering expertise.

Our Interconnect Networking Product Engineering team is looking for an excellent hardware engineer with strong coding, analysis, and debugging skills. This role requires a deep understanding of both hardware and software to develop robust test capabilities and processes. You will drive efficient integration and provide engineering support for production testing of cutting-edge product technology. You will help ensure reliable, efficient production tests with high coverage and strong outgoing product quality.

What youll be doing:

Characterize and develop test processes of advanced interconnect products.

Play a key role in the development and bring-up of advanced hardware test solutions supporting next-generation interconnect products.

Develop embedded software capabilities packages to support various of advanced power components and Digital\ Analog ICs

Cooperate with multidisciplinary design and analysis teams for bring up, performance optimization and seamless production integration.

Lead test solution innovations to reduce test time, costs and improve overall product quality.

Develop software solutions to find, debug, and resolve problems in the production and bring-up processes.

Collaborate with overseas manufacturing and mass-production teams to improve yield, test coverage, and capacity, and to resolve production issues.

Lead advanced studies of product behavior under a wide range of system and environmental conditions.

We are looking for a highly skilled Advanced Development Engineer to join the Software Architecture Team. In this hands-on role, you will shape the future of large‑scale data centers through advanced simulation, high‑scale telemetry, and next‑generation infrastructure solutions. You will work at the frontier of technology - exploring, prototyping, and proving new concepts - and turn them into scalable, production‑ready foundations. Your work will span large‑scale telemetry pipelines, data integrity at extreme scale, and advanced simulation frameworks used to model, validate, and optimize complex data‑center environments.

As part of the Architecture team, you will directly influence cross‑company platforms and long‑term technology direction, while actively contributing code, frameworks, and ideas. You will also have opportunities to participate in and contribute to open‑source projects and communities.

What you'll be doing:

Discover, evaluate, and prototype emerging technologies with a strong focus on simulation, scale, and system behavior modeling.

Design, implement, and evolve high‑scale software systems integrated across the full Data Center life‑cycle.

Build advanced simulation solutions to model data‑center behavior, telemetry flows, failure scenarios, and system performance at scale.

Define and expand large‑scale telemetry and observability pipelines, ensuring accuracy, consistency, and traceability of data.

Incorporate new and diverse data sources to continuously extend the capabilities of a centralized, petabyte‑scale Data Lake.

Collaborate closely with engineering, architecture, and research teams across us to translate business and technical requirements into robust, scalable solutions.

Work side‑by‑side with architects and data scientists to design, validate, and evolve data and simulation architectures.

Contribute to defining the architecture of next‑generation monitoring, analytics, and simulation platforms for hyperscale data centers.

Extend existing platforms and actively contribute code, designs, and leadership to Open Source projects and communities.

We are seeking an experienced Security Architect who has experience in confidential computing and attestation systems. The ideal candidate should have deep expertise in at least one leading confidential compute architecture and ideally in PCIe support around TDISP, IDE, SPDM. Strong knowledge of general system security, virtualization and hardware-enforced isolation primitives is essential.

What you'll be doing:
Lead, research, design, develop, and implement solutions for next-generation confidential computing network devices.
Develop novel hardware isolation mechanisms to provide defense in depth in the SoC.
Collaborate with external and internal hardware and software teams to implement and deliver the architecture.
Architectural modeling, validation, microarchitectural definition, and developing proofs-of-concept for secure platforms.

Youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. Join our team as a Senior Power and Performance Architect - Networking, influencing the future of our network systems.

What you'll be doing:
Develop, model, and validate groundbreaking power and performance optimization techniques for network fabrics, components (NICs, Switches), and systems. Collaborate closely with cross-functional teams including silicon design, system architects, software/firmware engineers, performance analysts, thermal engineers, and AI researchers to ensure end-to-end power and performance optimization. You will determine strategies that successfully implement flawless performance and power efficiency in our ambitious projects!

We are seeking a technical leader to define, craft, implement, and guide firmware architecture for reliability, availability, serviceability, and power management across next-generation Networking products and platforms. You will take a strong hands-on role, working with hardware, firmware, software, validation, customer engineering, and external partners to build robust, diagnosable, power-efficient systems for large-scale deployments.

What you'll be doing:

Define platform-level firmware architecture for RAS and power management across SoCs, accelerators, DPUs, servers, embedded systems, and data center platforms.

Own error detection, classification, containment, recovery, escalation, and reporting architecture.

Define firmware architecture for power sequencing, power states, reset flows, thermal and power fault handling, idle management, and recovery from power-related failures.

Create firmware specifications for hardware error handling, health monitoring, crash capture, telemetry, diagnostics, debug data, and field serviceability.

Define interfaces and contracts between firmware, hardware, operating systems, BMCs, management controllers, platform software, and cloud/service infrastructure.

Drive architecture reviews, tradeoff discussions, failure-mode analysis, validation strategy, and long-term RAS and power management roadmap planning.

Establish standards for error logs, event schemas, telemetry flows, recovery policies, service diagnostics, and production debug infrastructure.

Guide engineering teams through implementation, validation, silicon bring-up, platform integration, and production deployment of RAS and power management features.

Analyze customer and field failures, identify architectural gaps, and feed lessons learned into future platform designs.

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Engineering team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.



Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!



What youll be doing:

You will be in charge of state of the art Design for Test/ATPG flows and implementation.

Take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis.

Inventing and maintaining automation flows that provide the short test time to production.

The ideal candidate will possess strong problem-solving abilities and passion for developing innovative embedded solutions.

In this role, you will design, implement and maintain real-time embedded software for our next-generation wireless power products.

You will report directly to the VP of R&D.

Job Responsibilities:
Design, develop, improve, and maintain real-time embedded software from concept through production.
Define and implement firm architecture on ARM Cortex-M & STM8 microcontrollers.
Integrate real-time embedded software with external hardware components and complete system products.
Collaborate closely with hardware, systems and QA teams to ensure seamless integration and performance.
Participate in code reviews, debugging and system validation processes.
Create and maintain clear technical documentation for design and code.

Our team is looking for an FW engineer to design, develop, and implement complex SW modules for the production line. The integration will require cooperation with other teams and vendors abroad. Youll be part of a team developing complex and versatile hardware/software integrated solutions for mission-critical tasks in future products.
Are you a big-picture thinker who loves setting ambitious goals?
Do you have a passion for understanding how each line of code affects all the others?
Your dedication to cross-disciplinary collaboration will help develop groundbreaking technologies like iOS, macOS, watchOS, and tvOS. By crafting these distinct, holistic user experiences, youll continue to uphold and advance the excellence people expect from our devices.

Take part in SW design sessions (detailed designs involving system understanding), provide HLD and LLD documentation of central SW modules, participate in the coding of complex SW modules, debug complicated (system-wide) bugs, and lead HW-SW integrations.

Our Chip Design team is growing! Join our high-end product design team and help shape the next generation of advanced semiconductor solutions.
About us
The company has been delivering tens of millions of chips annually to leading tier-1 customers in the Security, Cloud, and Computing domains. We specialize in semi-custom, high-quality solutions, going above and beyond to meet our customers needs. Our Israel Design Center is fully self-contained, covering everything from product definition and architecture to design, software, validation, and TEST - meaning real ownership and no daily late-night calls across time zones We also pride ourselves on a warm, open culture where everyone knows each other, and every engineer can clearly see the impact of their work on the final silicon. We are looking for experienced Chip Design Engineers to join our team and take a key role in RTL design, new IP development, and SOC integration As part of the design team, you will be deeply involved in architectural exploration, protocol evaluation, and hands-on design work across multiple chip blocks. Responsibilities
* RTL design and implementation of new IPs
*  SOC integration and design ownership of chip subsystems
* Exploration and evaluation of new protocols and architectural solutions
* Close collaboration with architecture, verification, validation, software, and back-end teams
* Delivering high-quality, best-in-class RTL that meets performance, power, and area goals Why Join Us?
* Work on advanced, high-volume silicon products
* Real impact on end-to-end chip development
* Collaborative environment with strong technical ownership
* A stable yet agile organization with a human, people-first culture

our company's Automated Driving group in Haifa is looking for an experienced DFT Engineer.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC.
At our company's Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts - as it required by the Automotive and Safety related products market (ISO26262).

we are looking for an Emulation Engineer to join our Radar VLSI team and drive the development of next-generation ASIC Sensors.
We are developing best-in-class automotive radar solutions to complement our companys autonomous driving platform. Joining our expert team, you will leverage our companys unique assets to work on cutting-edge technology in a dynamic and challenging environment.
What will your job look like?
In this role, you will build high-end Emulation environments based on new designs. The position involves building and integrating complex components, working with cross-functional engineering teams, and developing systems that will change the way we drive.
We are looking for an engineer who thrives on challenges and is committed to engineering excellence while navigating complex constraints.
Lead Emulation development for the VLSI team.
Work closely with SW, Logic, and Verification engineers.
Serve as an expert matter for your domain, with full responsibility for driving and implementing improvements and new ideas.

Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to execution and full signoff. You will work closely with Design and Architecture teams on RTL modifications and design reviews to ensure seamless convergence.
Were looking for an Experienced Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner, leading the process from RTL to GDS .
Lead floorplan exploration in collaboration with Front-End and Architecture teams.
STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).