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Location: Haifa
Job Type: Full Time
We are looking for a hands-on engineer to join our Platform Architecture post-silicon team. This team analyzes and tunes the performance and power of Apple Silicon for the Mac, and takes the learnings and measurements to drive SoC architecture change for future chips. If you work comfortably across the hardware/software stack, and the idea to bring up brand-new chips that just arrived from the fab does not scare you but gets you excited, when we would like to hear from you.

You will join a multidisciplinary team of architecture, silicon design, and system software engineers driving the performance and energy efficiency of Apple SoCs. The work spans application software, system software, SoC architecture, and microarchitecture, and sits at the intersection of measured silicon behavior and forward-looking architecture definition. You will build a deep understanding of how current and planned Apple products behave end to end, and use it to influence both hardware and software direction.

Responsibilities
Tune and define SoC memory and fabric performance state controllers on unreleased silicon, and propose improved control and observability mechanisms for future generations.
Plan and execute architecture studies that drive performance and energy-efficiency decisions for future SoCs.
Build tools, workflows, and automation for repeatable analysis of simulated and measured data, including terabyte-scale traces from prototype devices.
Architect hardware features that improve workload characterization and enable robust online control of power and performance.
Debug complex interactions between system software and SoC hardware.
Assess the feasibility of future use cases, SoCs, and products.
Communicate findings across chip design, architecture, software, and system teams to enable data-driven decisions.
Requirements:
Minimum Qualifications
BSc, MSc, or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related field.
3+ years of experience in SoC performance analysis, architecture, or post-silicon characterization.
Hands-on post-silicon performance analysis on real hardware, including device capture and trace-based analysis.
Working knowledge of SoC memory subsystems, caches, fabric, or power management.
Proficiency in C++, Python, and the Unix shell.
Ability to work on-site full time at Haifa, Israel. This role requires regular hands-on access to lab hardware and prototype devices and is not eligible for remote work.

Preferred Qualifications
Tuning memory performance state controllers, DVFS, or power management policies on pre-production silicon.
Depth in one or more of: cache policy, quality of service, clock and power gating, or sleep state control.
Debugging system software and SoC interactions across the full stack.
Familiarity with processor or SoC design and validation flows, and with industry-standard benchmarks.
Use of AI coding tools (e.g., Claude Code) for development and automation.
A track record of influencing architecture decisions through data-driven analysis.
Effectiveness in ambiguous, fast-paced environments, working both independently and in a small team.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Requred SoC Power Architect, Cloud, Silicon
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Power Architect, you will not just design chips; you will define the energy efficiency of the infrastructure that powers our services worldwide.
In this role, you will be at the intersection of architecture, logic design, physical implementation, and system software. You will own the power architecture for next-generation custom SoCs (System on Chips), making critical trade-offs between performance, thermal constraints, and power delivery to build the most efficient computing platforms on the planet.
Responsibilities
Define and own the SoC power architecture, including complex power domains, clocking structures, and power delivery network (PDN) solutions to achieve optimal performance-per-watt.
Architect sophisticated power management policies, including dynamic voltage and frequency scaling (DVFS), power gating, and state strategies. Define the hardware/software interface for the Power management unit (PMU) and provide power management specifications.
Lead collaboration across architecture, RTL, physical design, packaging and validation teams to establish power budgets and specifications. Ensure power requirements are met from concept to tape-out.
Develop high-fidelity power and performance models to evaluate architectural features early in the design cycle. Drive pre-silicon power estimation and analysis to guide design decisions.
Lead post-silicon power analysis, correlating lab measurements with pre-silicon models to close the loop and improve future methodologies.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
10 years of experience in ASIC/SoC architecture or design with a focus on power optimizations.
Experience developing or using power and performance modeling tools to drive architectural trade-offs.
Experience in low-power design techniques (e.g., UPF/CPF, multi-voltage islands, power gating, clock gating, etc.) and on-chip power management IP.
Preferred qualifications:
Masters degree or PhD in Electrical Engineering, Computer Engineering, or a related field.
Experience in the design and analysis of full-chip power integrity, including interactions between clocking, reset, and power sequencing.
Experience with post-silicon bring-up, power calibration, thermal management, and debugging in a lab environment.
Experience with data center or server SoC power architecture and management requirements.
Experience with industry-standard EDA power tools (e.g., Conformal LP, Power-Artist, PrimeTime-PX, Joules) and simulation environments.
Familiarity with modern workload analysis (AI/ML, transcoding, networking) and their impact on SoC power profiles.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required SoC Chip Architect, Cloud, Silicon
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As an SoC Chip Architect, you will lead the definition of groundbreaking, high-performance custom silicon and multi-chiplet systems for our Cloud AI infrastructure. You will bridge the gap between hyperscale data center workload requirements and silicon implementation across various domains, collaborating with cross-functional partners to design scalable, energy-efficient, and feature-rich SoCs.
You will be part of a team pushing the boundaries of custom silicon engineering, architecting next-generation data center products that deliver industry-leading performance, low latency, and massive bandwidth for Cloud and our flagship AI services.
Responsibilities
Lead top-level SoC architecture across multiple disciplines, including IP architects, digital design, verification, physical design, validation, firmware, power management, security, and system software.
Architect and analyze complex multi-chiplet systems, including chip partitioning, die-to-die (D2D) interconnects, advanced packaging constraints, and high-performance on-chip fabrics (NoC).
Define top-level SoC subsystems, memory hierarchies, clock distribution, reset schemes, and power domains to ensure optimal system performance and operational efficiency.
Formulate end-to-end operational flows, latency models, and system throughput analyses for data center workloads.
Own the SoC architecture specification and lead it throughout the complete product life-cycle: concept, modeling, implementation, tape-out, and post-silicon bring-up.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
15 years of experience leading the architectural definition of high-performance SoCs, ASICs, or multi-chiplet systems from concept through production.
Experience architecting SoC interconnects, memory hierarchies, and system-level fabrics.
Experience writing, owning and maintaining comprehensive SoC architecture specifications.
Experience working across hardware, firmware, and system software boundaries with system-level reasoning.
Preferred qualifications:
Masters degree or PhD in Electrical Engineering or Computer Engineering.
Experience with AI workload analysis, their mapping across different data center system components, and optimizing hardware solutions to better serve them.
Experience scaling and optimizing high-performance AI accelerators, compute chiplets, or IO Hub SoCs for data center/cloud deployments.
Proven track record of architecting multi-chiplet systems utilizing cutting-edge silicon process technology and advanced packaging (2.5D/3D, D2D interfaces such as UCIe, BoW, or high-speed SerDes).
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required SoC Test Automation and Infrastructure Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our data centers are the most advanced in the world. In this role, you will help to manufacture the SoCs that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high-volume manufacturing at wafer fabrications and Outsourced Semiconductor Assembly and Test (OSATs). You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next-generation of chips.
You will help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices, drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs
You will have a strong understanding of IC flows, wafer processing, testing, qualification, diagnostics and failure analysis. You will work with various groups to deploy screening methodologies and flows for data processing, analytics and diagnostics. You will drive the release of cost effective production test solutions into mass production to hit yield and quality goals.
Responsibilities:
Provide tools, set the environment and create automation to silicon engineering (SiEng) teams, collaborate with Test, Product, quality and reliability (Q&R) and system-level test (SLT) teams.
Create smooth and effective ways to manage silicon engineering (SiEng) datastream to and from suppliers and internally, between different platforms, while optimizing formats and datalogs, convert per need.
Verify test solutions on pre-silicon models (simulation or emulation) and support Automated Test Equipment (ATE) test development setup and environment.
Develop test method for ATE platforms.
Provide pre and post silicon dashboards and indicators that will reflect the status, demonstrate progress and point on the gaps.
Requirements:
Minimum qualifications:
Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in test or product engineering, with experience in infrastructure and automation and people management experience.
Experience in pre-silicon validation, test content generation, ATE program development, big data handling and post-silicon enabling from New Product Introduction through high-volume manufacturing.
Experience with ASIC test methodologies (mbist, atpg, dft serdes, sensors).
Experience with Python, Java, C# or C/C++ and Advantest or Teradyne ATE platforms.
Preferred qualifications:
Masters in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
10 years of experience in test engineering, including product engineering.
Experience in ATE hardware design and proliferation: loadboards/probecards, handler kits, sockets, and thermal control solutions.
Experience with CPU/GPU SoC architecture, design, validation and debug.
Demonstrated expertise in developing automations for pre-silicon verification and post-silicon test-generation/test-program domains.
Inquisitive and motivated to venture into, and improve, all aspects of post-silicon testing from definition to realization.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Silicon Test and DFT Engineer, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Responsibilities
Collaborate with Architecture, Design and Verification teams to develop new product bring-up, validation, characterization, and qualification strategies and manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Verify test solutions on pre-silicon models (simulation or emulation) and develop Automated Test Equipment (ATE) test modules and binning flows.
Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) in preparation for high-volume manufacturing (HVM), working with ATE vendors and internal cross-functional teams.
Manage product sustainment support, including analyzing volume data, improving test time and yield, assessing test escapees and return merchandise authorizations (RMAs), localizing failures, implementing containment measures, and partnering with design, manufacturing, and quality and reliability teams to identify root causes and implement corrective actions.
Build tools, flows and methodologies to continuously improve and automate the testing life-cycle.
Requirements:
Minimum qualifications:
Bachelor's degree in Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience in test engineering.
Experience in pre-silicon validation, test content generation, automatic test equipment (ATE) program development, and post-silicon enabling from new product introduction (NPI) through high-volume manufacturing.
Experience with ASIC test methodologies (MBIST, ATPG, DFT, SerDes, and sensors).
Experience with Python, Java, C# or C/C++ and Advantest or Teradyne ATE platforms.
Preferred qualifications:
Masters in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
10 years of experience in test engineering, including product engineering.
Experience with CPU/GPU SoC architecture, design, validation and debug.
Experience in advanced testing methodologies and data analysis, including system to tester correlation, yield and test time analysis and improvement, etc.
Demonstrated expertise in developing automations for pre-silicon verification and post-silicon test-generation/test-program domains.
Inquisitive and motivated to venture into, and improve, all aspects of post-silicon testing from definition to realization.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Power and Signal Integrity Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
You'll set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners.
The ML, Systems, & Cloud AI (MSCA) organization designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all services (Search, YouTube, etc.) and Cloud.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities:
Design and optimize power distribution networks (PDN) across chip, package, and board levels. This includes managing power/ground planes, decoupling capacitors, and power gating strategies.
Conduct both pre-layout and post-layout power integrity simulations to analyze power and ground noise (SSN/SSO), voltage drops (IR drop), and electromagnetic interference (EMI).
Implement and verify low-power design methodologies, such as multi-voltage designs and clock gating, using power intent formats like UPF/CPF.
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR), Spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.
Requirements:
Minimum qualifications:
Bachelor's degree in Mechanical, Electrical Engineering, Material Science, or equivalent practical experience.
5 years of experience in signal or power integrity or hardware design.
Preferred qualifications:
Experience with industry-standard Electronic Design Automation (EDA) tools for simulation and layout (e.g., Cadence Sigrity/Allegro, Ansys HFSS/PowerDC/Q3D, Keysight ADS, Synopsys HSPICE).
Proficiency in scripting languages such as Python, Perl, or Tcl for flow automation and data analysis.
Familiarity with high-speed testing equipment like VNAs, TDRs, and oscilloscopes for measurement and validation.
Knowledge of circuit analysis, electromagnetics, and transmission line theory.
This position is open to all candidates.
 
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Location: Herzliya and Haifa
Job Type: Full Time
We're seeking a passionate and skilled Embedded Firmware Engineer to play a pivotal role in delivering the next generation of us. In this highly visible position, you'll be at the intersection of hardware and software, collaborating closely with logic designers to deeply understand system-level operations and performance requirements for hardware validation. In this role, you will develop critical low-level embedded firmware specifically designed to validate hardware functionality, ensure conformance, and drive performance during the bring-up and testing phases of new silicon. This involves designing, developing, and integrating complex drivers, diagnostic tests, and infrastructure essential for SoC bring-up, post-silicon validation, and debugging activities. Ultimately, you'll lead hands-on firmware development, system-level validation, and problem-solving at the hardware-software interface in a dynamic, collaborative environment, with your work directly enabling the successful launch of future products by ensuring our silicon meets the highest standards.
Requirements:
Minimum Qualifications
3+ years of experience in embedded firmware development within Real-Time (RT) or Embedded environments.
Strong proficiency in C, with a deep understanding of hardware-software interaction.
Hands-on expertise with Hardware-Software integrations, particularly for silicon validation and bring-up.
Exceptional debugging skills at the firmware and hardware level.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.

Preferred Qualifications
Experience with pre-silicon and post-silicon validation methodologies.
Familiarity with CPU architectures (e.g., ARM) and low-level system programming.
Direct experience with System-on-Chip (SoC) development or validation.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SOC and IP Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
Experience with reasoning synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power and design techniques.
Experience in reasoning design and debug with Design Verification (DV).
Preferred qualifications:
Experience with a scripting language like Python or Perl.
Experience with design sign-off and quality tools (e.g., Lint, clock domain crossing (CDC), etc.).
Knowledge of System on a chip (SOC) architecture and assertion-based formal verification.
Knowledge of design techniques.
Knowledge in one of these areas: Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), Double Data Rate SDRAM (DDR), Advanced Extensible Interface (AXI), ARM processors.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SoC and IP Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
Perform Register-Transfer Level (RTL) coding (coding and debug in Verilog, SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure activities.
Contribute to test plan and coverage analysis of the block and SoC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.).
Experience with SoC or IP architecture.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Knowledge of high-performance and low-power design techniques, assertion-based formal verification, Field-Programmable Gate Array (FPGA) and emulation platforms, and SoC architecture.
Knowledge in one of the following areas such as Double Data Rate (DDR)/Low Power Double Data Rate (LPDDR), High-bandwidth memory (HBM).
Excellent problem-solving and debugging skills.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Physical Design Engineer, SoC Static Timing Analysis
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. In this role, you will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering exceptional performance, efficiency, and integration.
Responsibilities
Drive the sign-off timing convergence for high-performance designs.
Set up the timing constraints, define the overall static timing analysis (STA) methodology, set up the STA infrastructure and sign-off convergence flows, and work closely with block owners throughout the project for sign-off timing convergence.
Work with logic designers to drive architectural feasibility studies, develop timing, and explore RTL/design trade-offs for physical design closure.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience.
8 years of Physical Design experience including 5 years of experience with Static Timing Analysis (STA), including sign-off corner definitions, process margining, interface timing constraints, timing convergence, and setting frequency goals with technology scaling.
Experience in constraints development for subsystems or full System-on-Chip (SoC) architectures.
Preferred qualifications:
Proficiency with scripting languages commonly used in hardware automation (e.g., Tcl, Python, or Perl).
Deep familiarity with ASIC physical design flows and methodologies, including synthesis, place and route (P&R), formal verification, and clock domain crossing (CDC).
Solid fundamental knowledge of semiconductor device physics and transistor characteristics.
This position is open to all candidates.
 
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Herzliya and Haifa
Job Type: Full Time
We are seeking a software engineer to build high-performance software models of advanced SoC designs and to help bridge the gap between Software and Hardware, influencing performance improvements, power efficiency, security, and the programming ease of Apple products.
Responsibilities
In this role, you will:
Develop software systems and tools used to bring up the future OS on future SoCs.
Support kernel and driver development on future processor & SoC models.
Work closely with software and hardware teams across product and research groups.
Promote new opportunities and techniques with other groups.
Requirements:
Minimum Qualifications
Experience with programming (C++/C) and scripting skills (Python). (MSc graduates may be considered without prior industry experience)
Background in low-level software, operating systems, or compilers.
Experience developing and debugging large, complex system software.
Experience with concurrent and parallel programming.
Knowledge of ARM and/or X86 architecture.

Preferred Qualifications
Degree in Computer Science or Computer Engineering.
Experience with kernel, driver and firmware development.
Experience with modeling and simulation.
Assembly experience.
Knowledge of modern SoC architectures.
Experience collaborating with cross-functional teams to achieve scheduled milestones.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8847760
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