דרושים » חומרה » Micro-Architect

Required Micro-Architect
Description
We are a global leader in control systems for quantum computing, a field on the verge of exponential growth.
Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands.
At the core of QM lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers.
Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
Join our cutting-edge hardware development team as Micro-Architect and play a key role in defining and implementing the micro-architecture of advanced digital logic components.
What You'll Do:
Define and develop micro-architecture for complex logic blocks - from concept through high-quality RTL implementation
Collaborate closely with architecture, verification, design and software design teams
Write clear and detailed design specifications and drive architectural trade-off analysis
Optimize for performance and area
Contribute to innovation, methodology improvements, and technical leadership within the team.

Required Micro-Architect, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Lead Design Activities at IPs, SubSystems(S.S) and SoC.
Define the block-level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up, as well as test plan development and coverage analysis for block and SOC-level verification.
Communicate and collaborate with multi-disciplined and multi-site teams.

Required Senior RTL Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use Application-Specific Integrated Circuit (ASIC) design to be part of a team that creates the System on a Chip (SoC) design cycle from start to finish. You will collaborate with design and verification engineers in projects, creating architecture definitions with Register-Transfer Level (RTL) coding, and running block level simulations. You will contribute in ASIC designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and more to specify and deliver high quality SoC/RTL. You will also solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with performance, power, and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our platforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Lead a complex ASIC subsystem.
Understand how the subsystem interacts with software and other ASIC subsystems to implement groundbreaking data center.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

Required RTL Design Technical Lead, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will contribute in all phases of Application-Specific Integrated Circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.
Responsibilities:
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

We are seeking for a passionate and skilled Validation Engineer to join our core R&D team. As a Validation Engineer, you'll play a critical role in ensuring the quality, reliability, and performance of our state-of-the-art quantum control systems. You will design, develop, and execute validation plans for complex hardware-software systems, contributing directly to the advancement of quantum technologies.
This role is ideal for engineers with good programming skills, a strong technical culture, and a passion for working at the intersection of software, hardware, and quantum science.
Main Responsibilities:
Design and Implement Validation Methods: Design, implement and execute comprehensive validation test plans for our quantum control platforms and solutions
Automated Tests and Automation Frameworks: Contribute to the development of automated testing infrastructures to streamline validation processes and implement system tests based on the defined test plans
AI/ LLM Tools: Apply AI/LLM tools to accelerate test code generation and continuously improve the validation toolchain, driving measurable gains in engineering productivity
Data Analysis: Collect, interpret, and document data from system tests/experiments to assess system performance and identify areas for improvement
System Debugging & Troubleshooting: Identify, reproduce, and analyze issues across system components with other engineering teams
Collaborate Across Teams: Collaborate closely with R&D and product teams to define test coverage and quality acceptance criteria
Release & Quality Assurance Process: Participate in regression testing and CI/CD for new feature rollouts and product releases
Maintain and Improve Test Setups: Oversee the setup, calibration, and enhancement of test equipment and environments

As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.

As a Senior ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams

Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities

Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration

As we expand our presence in Israel, we're seeking a talented Staff / Principal ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.

As a Staff / Principal ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support.
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions.
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams.

Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient.
Apply design techniques to meet PPA (Power, Performance, Area) targets.
Contribute to design quality through verification and validation activities.

Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives.
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter.
Collaborate effectively across teams to ensure seamless integration.

Required Machine Learning Hardware Architect, Hardware, Software Co-Design, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Machine Learning Hardware Architect within the Co-design team, you will serve as a technical lead bridging model architecture innovation and next-generation hardware design. Operating at the highest levels of AI research and engineering, you will define the goal and architectural roadmap for our future machine learning serving and training capabilities. You will guide the integration of ML research such as massive-scale foundation models with advanced silicon architectures to create industry-leading, high-performance, and power-efficient accelerators.
Responsibilities:
Define and drive the technical roadmap and architecture for the hardware/software stack to ensure exceptional performance for ML models. Act as the technical liaison across research, software, and hardware teams, steering model architecture innovation to maximize scaling, quality, and hardware efficiency.
Architect next-generation configurable simulation frameworks and performance models, setting the organizational standard for evaluating complex microarchitectural decisions. Drive high-stakes choices regarding Power, Performance, Area (PPA) and buildability for future chip and system architectures, expertly balancing long-term technological trends with strict product delivery timelines.
Guide system-level performance analysis across highly distributed ML systems, innovating new methodologies to optimize and balance compute, memory bandwidth, and inter-chip network requirements. Their leadership will directly shape the future of high-performance AI infrastructure and hardware-software co-design.
Manage cross-functional partnerships across hardware, compiler development and ML teams.

We are looking for a highly experienced Quantum Control Systems Engineer (Application Validation Team) who embodies ambition and positivity. Someone who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfill the evolving needs of our expanding customer base.
As a Quantum Control Systems Engineer on the Application Validation Team, you will be responsible for validating the software and hardware systems that drive quantum computing operations, ensuring that programs ranging from calibrations to error correction procedures perform as expected on all our quantum controller hardware. This includes designing, implementing, and testing scalable software and hardware frameworks across various qubit types, as well as developing tools that support the validation and execution of control software across different configurations and execution platforms.
Your role will also involve developing a robust software infrastructure that automates the validation process, integrates with real hardware systems, and supports continuous integration (CI) and continuous deployment (CD) pipelines.
This is an exciting opportunity to work at the forefront of quantum computing technology while ensuring the performance, reliability, and scalability of cutting-edge control systems.
Join us in this exciting journey to redefine the future of quantum computing.
Responsibilities:
Quantum Computing Routine Validation: Validate quantum computing programs on our quantum controllers, including calibration procedures, error correction routines, and other algorithms, ensuring they meet the required performance standards.
Scalable Routine Design: Design and implement scalable quantum routines in Qua and other quantum computing languages, optimizing various qubit types and quantum computing architectures.
Framework Development: Develop tools and frameworks that support validation, ensuring scalability and integration into our hardware and software development process.
Automated Testing and CI/CD Integration: Build and maintain automated testing systems, incorporating CI/CD processes to ensure seamless integration and validation of quantum control software on real hardware.
Data Analysis: Analyze measurement data from quantum controllers, using this data to improve implementations across the whole software stack.
Cross-Functional Collaboration: Work closely with quantum physicists, customers software engineers, and hardware engineers to troubleshoot issues, refine quantum routines, and ensure the overall system's performance.

We are looking for a highly experienced Quantum Control Systems Engineer (Application Validation Team) who embodies ambition and positivity. Someone who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfill the evolving needs of our expanding customer base.
As a Quantum Control Systems Engineer on the Application Validation Team, you will be responsible for validating the software and hardware systems that drive quantum computing operations, ensuring that programs ranging from calibrations to error correction procedures perform as expected on all our quantum controller hardware. This includes designing, implementing, and testing scalable software and hardware frameworks across various qubit types, as well as developing tools that support the validation and execution of control software across different configurations and execution platforms.
Your role will also involve developing a robust software infrastructure that automates the validation process, integrates with real hardware systems, and supports continuous integration (CI) and continuous deployment (CD) pipelines.
This is an exciting opportunity to work at the forefront of quantum computing technology while ensuring the performance, reliability, and scalability of cutting-edge control systems.
Join us in this exciting journey to redefine the future of quantum computing.
Responsibilities:
Quantum Computing Routine Validation: Validate quantum computing programs on our quantum controllers, including calibration procedures, error correction routines, and other algorithms, ensuring they meet the required performance standards.
Scalable Routine Design: Design and implement scalable quantum routines in Qua and other quantum computing languages, optimizing various qubit types and quantum computing architectures.
Framework Development: Develop tools and frameworks that support validation, ensuring scalability and integration into our hardware and software development process.
Automated Testing and CI/CD Integration: Build and maintain automated testing systems, incorporating CI/CD processes to ensure seamless integration and validation of quantum control software on real hardware.
Data Analysis: Analyze measurement data from quantum controllers, using this data to improve implementations across the whole software stack.
Cross-Functional Collaboration: Work closely with quantum physicists, customers software engineers, and hardware engineers to troubleshoot issues, refine quantum routines, and ensure the overall system's performance.