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We are looking for a Senior Software Engineer to join the DOCA SDK Verification team. The DOCA SDK enables developers to rapidly create applications and services on top of our BlueField data processing units (DPUs), leveraging industry-standard APIs. With DOCA, developers can deliver breakthrough networking, security, and storage performance by harnessing the power of our DPUs.

What you will be doing:
As a Senior Software Engineer in the DOCA verification team, you will play a key role in designing and developing the verification infrastructure for the DOCA SDK. This infrastructure is a complex system that executes thousands of tests every night across multiple hardware platforms and configurations. It includes mechanisms for error handling and fault recovery, while test results are stored, analyzed using advanced tools, and presented through live dashboards and reports. Your expertise in building robust and efficient verification systems will be critical to ensuring the reliability and quality of our software.

We are looking for an excellent Senior Firmware Engineer to join the FW group in Tel-Aviv / Raanana. As a Senior Engineer you will be taking part in designing, implementing and leading major development firmware features, delivering the next-generation data center products who lead the AI revolution.

The Firmware team develops cutting-edge networking features for cloud, HPC and AI. We drive the data growth of the worlds biggest companies. With talented engineers around the globe, the work environment is dynamic, meaningful, and fast-paced. Are you ready for the challenge?

What you will be doing:

Collaborate with architecture and different software design teams as part of the software development lifecycle.

Design and implement new features in the core of our firmware.

Work in pre and post-silicon development environments of next-generation networking products.

Gain a deep understanding of system debugging, networking technology, and stacks, as well as the HW/FW/SW relationship.

Innovate! Bring our FW NVLINK products to shine in customers view.

We are We are seeking a Senior Switch Silicon Security Architect to define end-to-end security across switch silicon, firmware, networking protocols, and management stacks. Working with architecture, engineering, and product teams, this role will shape security from early design through validation, manufacturing, and deployment.

What you'll be doing:

Research, design, and drive the implementation of hardware and software security architectures for switch platforms that meet internal requirements, customer needs, and industry standards.

Develop threat models and define end-to-end security architectures for hyperscale networking solutions spanning silicon, firmware, high-performance networking protocols, and management stacks.

Partner across us with hardware, software, research, and product teams to shape the strategic direction of switch silicon and fabric-level security.

Define and drive multi-generation security roadmaps for switch silicon, networking protocols, and fabric-level solutions.

Engage directly with customers to understand their security requirements and translate them into switch silicon and system architectures that address both component and solution-level needs.

Represent us in industry standards bodies and collaborate with external partners to shape emerging security standards and drive interoperability across silicon and networking ecosystems.

As member of the DV CAD team, you have the opportunity to impact our engineers who develop next generation of our products!
You will be responsible for developing software solutions used by thousands of DV engineers globally. You will be supporting design process of all chip families we make (iPhone, iPad, Mac, our Watch and more), and your work will help streamline this complex process. This role combines DV knowledge alongside modern software engineering practices. Your work will be very diverse, and you will have broad impact contributing to the success of us.


You will develop and drive software development of multiple tools across the DV space, including cloud-native services, GUI, LLM harness, CI/CD. Your work will span from software development and architecture to collaborating with DV engineers, working with EDA vendors, and supporting critical project milestones.

Responsibilities
Developing and maintaining LLM harness for agentic DV workflows, and being responsible for benchmarking and improving accuracy of agentic workflows.
Building and managing cloud-native services running on k8s, including CI/CD, containerization, alerting, databases, GUI and monitoring.
Communication with DV stakeholders and working to understand user requirements.
Writing and maintaining Python scripts used as part of design simulation flows.
Supporting multiple projects simultaneously.

We are looking for a SQA Engineer to join our team!

Key Responsibilities:
Design, develop, and maintain automated tests for embedded products using C# and NUnit.
Execute manual and automated test plans, analyze results, and report defects.
Prepare and maintain test documentation, including STP, STD, and STR.
Investigate, reproduce, and track software defects through resolution.
Collaborate closely with R&D, software developers, and cross-functional teams to ensure product quality.
Participate in test planning, design reviews, and quality improvement activities.
Support continuous improvement of QA processes, methodologies, and automation frameworks.
Report to the SQA Team Leader.

Our Switch ASIC group is seeking a top-tier ASIC technical manager to lead the development of our next-generation ASICs. Join us in shaping the future of technology! As an ASIC Project Lead, you will manage the pre-silicon development of NVIDIA's most advanced and complex switch ASICs - from concept to tape-out - and drive the chip through power-on and qualification to production release. You will collaborate with a cross-disciplinary team, interacting with unit-level ASIC, Physical Design, CAD, Package Design, Firmware & Software, DFT, System Design, Analog Design, and other specialized teams.


What you'll be doing:
Development Management: Lead the ASIC development from concept and architecture stages through micro-architecture, design, verification, and physical design until tape-out.
Post-Silicon Execution: Drive chip power-on, bring-up, and qualification to production release.
Execution Plans: Define and implement execution plans in collaboration with cross-discipline leaders in unit-level, full-chip, physical design, and firmware/software emulation.
Roadmap Definition: Contribute to the definition of NVIDIA's switch ASIC roadmap.

We are seeking an AI Networking Architect to join the Networking Research Group. This role bridges the gap between emerging AI workloads and the data center infrastructure that powers them, working at the intersection of AI applications, distributed systems, networking hardware, and software architecture. You will join a focused team of multidisciplinary engineers driving AI workload optimization through deep application understanding, network analysis, and end-to-end systems thinking. Your insights will directly shape our products across the full stack - from applications and software libraries to hardware architecture and physical design.


What you'll be doing:
Model the performance of complex AI workloads to identify bottlenecks and recommend system-level optimizations.
Analyze new AI models, distributed training techniques, and inference workloads to understand their infrastructure requirements.
Build simulation and hardware platforms, run real AI workloads on them, and develop analytical tools to evaluate trade-offs across compute, memory, storage, and network behavior.
Translate research insights and workload behavior into actionable software, xhardware, and networking architecture requirements.
Partner with architecture, software, and product teams to influence our future networking and AI infrastructure roadmaps.
Drive architectural innovation by applying deep workload analysis to production machine learning frameworks.

We are seeking a highly skilled and versatile Performance Research and Analysis Manager to join our Performance Group. This role will drive end-to-end performance strategy and execution for our next-generation data centers and solutions based on GPU systems, NIC, Switch, DPU and Networking technologies. The ideal candidate will oversee, evaluating, and optimizing end-to-end AI GPU cluster-level performance for scaling out large scale distributed training and inference jobs communication. The role will focus heavily on RDMA, Networking Protocols, Collective Communication, Congestion Control, and Load Balancing algorithms. Secondarily, you will lead our DPUs and Storage technologies for N-S use cases to support AI Inference jobs. Third, you will drive our Performance Dashboards and Observability for cluster-level performance analysis from a stream line telemetry across NICs, Switches, GPUs, and NVlink.

What you'll be doing:

Drive end-to-end performance strategy, characterization, test plans, and optimization for our next-generation AI GPU clusters, focusing on large-scale distributed training and inference workloads.

Deeply evaluate and optimize our Networking core technologies performance, including RDMA/PRDMA, networking protocols, collective communication (NCCL), congestion control, and load-balancing algorithms.

Work on performance research and analysis of our DPUs and storage technologies in North-South (N-S) use cases and deployment scenarios to maximize performance and efficiency for AI inference jobs.

Drive the strategy for performance observability and dashboards across our next-generation data center solutions and supercomputers by leveraging scalable, streamlined telemetry pipelines to build performance dashboards and automated analytics based on real-time performance metrics across NICs, Switches, GPUs, and NVLink boundaries.

Perform deep root-cause analysis (RCA) on complex multi-node performance bottlenecks, driving actionable mitigation plans across hardware, firmware, and software teams.

We are looking for a Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams.

Key Responsibilities
Perform hands-on post-silicon validation
Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability.
Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.
Drive complex issues from initial failure through root-cause analysis and final resolution.
Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.
Validate PCIe functionality across different generations, platforms, configurations, and operating conditions.
Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.
Develop automation to improve validation coverage, debug efficiency, and regression testing.